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检索条件"任意字段=Euromicro Conference on Parallel, Distributed and Network-Based Processing"

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xENoC - an experimental network-on-chip environment for parallel distributed computing on NoC-based MPSoC architectures

xENoC - an experimental network-on-chip environment for para...

引用

16th euromicro International conference on parallel, distributed and network-based processing

作者： Joven, Jaume Font-Bach, Oriol Castells-Rufas, David Martinez, Ricardo Teres, Lluis Carrabina, Jordi MISE CEPHIS Campus UABBldg Q ETSE Bellaterra 08193 Spain IMB CNM Bellaterra 08193 Spain CTTC Castelldefels 08860 Spain

ISBN: (纸本)9780769530895

This paper describes xENoC, an automatic and component re-use HW-SW environment to build simulatable and synthesizable network-on-Chip-based MPSoC architectures. xENoC is based on a tool, named NoCWizard, which uses an eXtensible Markup Language (XML) specification, and a set of modularized components and templates to generate many types of NoC instances by using Verilog HDL. This NoC models can be customized in terms of topology, tile location/mapping, RNIs generation, different types of routers, FIFO and packet/flit sizes, by simply modifying the XML specifications. Furthermore, xENoC is also composed of software components, i.e. RNI drivers and a parallel programming model, embedded Message Passing Interface (eMPI), which let us to carry out a complete HW-SW co-design methodology to design distributed-memory NoC-based MPSoCs parallel applications. Through xENoC different distributed-memory NoC-based MPSoCs designs have been created simulated and prototyped in physical platforms (e.g. FPGA boards), and some parallel multiprocessor test traffic applications are running there as system level demonstrators.

关键词： network-on-chip

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Memory-aware tree partitioning on homogeneous platforms 26

Memory-aware tree partitioning on homogeneous platforms

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26th euromicro International conference on parallel, distributed, and network-based processing (PDP)

作者： Gou, Changjiang Benoit, Anne Marchal, Loris Ecole Normale Super Lyon Lab LIP Lyon France ECNU Shanghai Peoples R China

ISBN: (纸本)9781538649756

Scientific applications are commonly modeled as the processing of directed acyclic graphs of tasks, and for some of them, the graph takes the special form of a rooted tree. This tree expresses both the computational dependencies between tasks and their storage requirements. The problem of scheduling/traversing such a tree on a single processor to minimize its memory footprint has already been widely studied. Hence, we move to parallel processing and study how to partition the tree for a homogeneous multiprocessor platform, where each processor is equipped with its own memory. We formally state the problem of partitioning the tree into subtrees such that each subtree can be processed on a single processor and the total resulting processing time is minimized. We prove that the problem is NP-complete, and we design polynomial-time heuristics to address it. An extensive set of simulations demonstrates the usefulness of these heuristics. © 2018 IEEE.

关键词： memory aware parallel processing tree partitioning

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Research on the Design and Implementation of Financial ERP System based on Grid Algorithm 25

Research on the Design and Implementation of Financial ERP S...

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Proceedings of the 2025 4th International conference on Big Data, Information and Computer network

作者： Xinyue Zhang Zhe Yang Shuai Zhang Beiing China-Power Information Technology co. LTD Beijing China

ISBN: (纸本)9798400712425

Finance informatization is an important method that helps managers in companies to enhance the decision-making quality along with their efficiency. The finance ERP system enriched with the help of the grid algorithms facilitates data analytics and the following of funds, with the assistance of such computational resources, the status of which is that the deployment of computational resources is done effectively and the task scheduling model is efficient. During looking at these grid algorithms on a more detailed level, these are results that were obtained when classification methods such as dynamic scheduling algorithms and load balancing algorithms were performed, the ones of which can particularly be used for parallel and distributed computing along with a multitude of services or enhancing the financial system performance. An experiment's design included explicit environmental setups that were outlined and a myriad of test datasets, which facilitated the assessment of comparative efficiency. The response time and processing efficiency the ERP system achieves using grid algorithms are the main causes of enhanced system performance metrics (far beyond the traditional thresholds). Besides the smoothness and cost-effectiveness of the system, the new system will result in an economic advantage in the market for a design concept that also will provide enterprises with the outline of and help in the implementation of the system that will solve a variety of financial issues they face. The study result indicates refreshed views and suggestions for the future economic management, the result of which will be efficient financial decisions and better use of the resources.

关键词： Grid algorithm

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parallelizing Soft-Synths with Soft Real-Time Requirements 25

Parallelizing Soft-Synths with Soft Real-Time Requirements

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25th euromicro International conference on parallel, distributed and network-based processing (PDP)

作者： Cameron, Ede Goswami, Dhrubajyoti Concordia Univ Dept Comp Sci & Software Engn Montreal PQ Canada

ISBN: (纸本)9781509060580

Though parallel processing of applications related to video processing and rendering are widespread, parallel processing of audio synthesis software (also known as soft-synths) is not much researched. This paper addresses our research and experiments in parallelizing digital audio synthesizers on a commodity multicore platform where these synthesizers are most commonly used. Soft real-time requirements and overheads of parallelization are two of the competing forces in this research. As a case study, the ALSA (Advanced Linux Sound Architecture) Modular audio Synthesizer (AMS) is evaluated. AMS employs a modular approach to digital music synthesis, is often part of a standard Linux installation package, has a GUI for user interactions, and like other audio synthesizers it has a soft real-time requirement. The main intentions of parallelization are for enhancing throughput and hence stability, whereby more complex and higher quality audio can be generated. The GUI based interactive approach adds an extra challenge of a dynamic call graph that can change on-the-fly. The paper compares the pros and cons of the different techniques adopted, and highlights the advantages of parallelization. The lessons learnt can also be used in parallelizing other existing audio synthesizers and designing new parallel synthesizers from scratch.

关键词： digital audio synthesizers ALSA modular synthesizer synthesized digital music parallel processing

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Efficient Wavefront parallel processing for HEVC CABAC Decoding 28

Efficient Wavefront Parallel Processing for HEVC CABAC Decod...

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28th euromicro International conference on parallel, distributed and network-based processing (PDP)

作者： Habermann, P. Juurlink, B. Chi, C. C. Alvarez-Mesa, M. TU Berlin Embedded Syst Architecture Berlin Germany Spin Digital Video Technol GmbH Berlin Germany

ISBN: (纸本)9781728165820

Context-based Adaptive Binary Arithmetic Coding (CABAC) is the only compute-intensive task in the High Efficiency Video Coding (HEVC) Standard that does not contain significant data-level parallelism. As a result, it is often a throughput bottleneck for the overall decoding process, especially for high-quality videos. Consequently, the use of high-level parallelization techniques is inevitable to reach throughput requirements for CABAC decoding. Multiple high-level parallelization tools are specified in HEVC, amongst which Wavefront parallel processing (WPP) has only small losses in coding efficiency. However, it lacks in parallel efficiency due to a ramp-up and -down in active parallel threads within a frame. This is a serious problem for systems that cannot process multiple frames at the same time due to performance or memory constraints (e.g. mobile devices), and also for low-delay applications such as video conferencing. To address this issue, we present three improved WPP implementations for HEVC CABAC decoding. They differ in the granularity at which dependency checks are performed. The improvement comes from increased parallel efficiency of the WPP implementation while using the same number of threads as conventional WPP. The proposed implementations allow speedups up to 1.83 x with very little implementation overhead.

关键词： HEVC H.265 CABAC Wavefront parallel processing

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parallelizing Broad Phase Collision Detection Algorithms for Sampling based Path Planners

Parallelizing Broad Phase Collision Detection Algorithms for...

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21st euromicro International conference on parallel, distributed, and network-based processing (PDP)

作者： Geleri, Fuat Tosun, Oguz Topcuoglu, Haluk Bogazici Univ Dept Comp Engn TR-34342 Istanbul Turkey Marmara Univ Comp Engn Dept TR-34722 Istanbul Turkey

ISBN: (纸本)9780769549392;9781467353212

Collision checking takes most of the time in sampling based path planning algorithms. When the scene gets crowded, more samples are needed and the probability decreases to find a collision free sample. Broad phase algorithms are designed to eliminate obviously collision free samples, so narrow phase algorithms can concentrate on fewer samples suspected to be in collision. In this study, we compare the performance of two broad phase algorithms implemented on both CPU and GPU. A novel technique is proposed to provide load balancing and efficient cache utilization on Bounding Sphere Collision Detection algorithm. Furthermore, Thrust library is extensively utilized on Sweep and Prune (SAP) algorithm. Our experimental results indicate speedups up to 103 times faster for GPU-based SAP algorithm and 134 times faster for GPU-based Bounding Sphere algorithm, compared to CPU implementations. This may allow using sampling based path planning algorithms for scenes with many robots.

关键词： collision detection broad phase OpenMP CUDA

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Scheduling Metric-Space Queries processing on Multi-Core Processors

Scheduling Metric-Space Queries Processing on Multi-Core Pro...

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18th euromicro International conference on parallel, distributed and network-based processing (PDP)

作者： Gil-Costa, Veronica Barrientos, Ricardo J. Marin, Mauricio Bonacic, Carolina Univ San Luis DCC San Luis Argentina Yahoo Res Latin Amer Santa Clara CA USA Univ Chile DCC Santiago Chile Univ Complutense Madrid ArTeCS Grp Madrid Spain

ISBN: (纸本)9780769539393

This paper proposes a strategy to organize metric-space query processing in multi-core search nodes as understood in the context of search engines running on clusters of computers. The strategy is applied in each search node to process all active queries visiting the node as part of their solution which, in general, for each query is computed from the contribution of each search node. When query traffic is high enough, the proposed strategy assigns one thread to each query and lets them work in a fully asynchronous manner. When query traffic is moderate or low, some threads start to idle so they are put to work on queries being processed by other threads. The strategy solves the associated synchronization problem among threads by switching query processing into a bulk-synchronous mode of operation. This simplifies the dynamic re-organization of threads and overheads are very small with the advantage that the overall work-load is evenly distributed across all threads.

关键词： Query processing

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Static load distribution for communication intensive parallel computing in multiclusters

Static load distribution for communication intensive paralle...

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16th euromicro International conference on parallel, distributed and network-based processing

作者： Heien, Eric M. Fujimoto, Noriyuki Hagihara, Kenichi Osaka Univ Grad Sch Informat Sci & Technol Osaka 5608531 Japan

ISBN: (纸本)9780769530895

In this paper, we examine load distributions to minimize total run time in multi-cluster parallel computing algorithms by applying divisible load theory techniques. Even with homogeneous processor speeds, parallel computations in multi-clusters that evenly assign load can run at less than maximum efficiency due to communication heterogeneity. Using a modified version of the LogP parallel computing model, we propose a general technique of assigning load among multiple clusters to minimize the time each processor spends waiting. This technique is used to determine optimal load distribution for spin glass simulation and parallel bucket sort in multi-cluster systems. It also allows fast analysis of the effects of adding processors or clusters to the computation. We experimentally demonstrate the accuracy of our model, and show how it eliminates wait time in multi-cluster parallel computations. Using load distributions derived from our technique results in an execution time decrease of up to 50%, depending on the degree of heterogeneity among clusters and communication characteristics of the computation.

关键词： parallel processing systems

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A Secure distributed Framework for Agglomerative Hierarchical Clustering Construction 26

A Secure Distributed Framework for Agglomerative Hierarchica...

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26th euromicro International conference on parallel, distributed, and network-based processing (PDP)

作者： Hamidi, Mona Sheikhalishahi, Mina Martinelli, Fabio Univ Siena Dipartimento Ingn Informaz & Sci Matemat Siena Italy CNR Ist Informat & Telemat Pisa Italy

ISBN: (纸本)9781538649756

This paper presents a general framework for constructing any agglomerative hierarchical clustering algorithm over partitioned data. It is assumed that data is distributed between two (or more) parties horizontally, such that for mutual benefits the participated parties are willing to identify the clusters' structure on their data as a whole, but for privacy restrictions, they avoid to share the original datasets. To this end, in this study, we propose general algorithms based on secure scalar product and secure hamming distance computation to securely compute the desired criteria for shaping the clusters' scheme. The proposed approach covers all possible secure agglomerative hierarchical clustering construction when data is distributed between two (or more) parties, including both numerical and categorical data.

关键词： Privacy Hierarchical Clustering Secure Two-Party Computation Collaborative Clustering

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A Dynamic Task-based D3Q19 Lattice-Boltzmann Method for Heterogeneous Architectures 27

A Dynamic Task-based D3Q19 Lattice-Boltzmann Method for Hete...

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27th euromicro International conference on parallel, distributed and network-based processing (PDP)

作者： Lima, Joao V. F. Freytag, Gabriel Pinto, Vinicius Garcia Schepke, Claudio Navaux, Philippe O. A. Univ Fed Rio Grande do Sul Porto Alegre RS Brazil Univ Fed Santa Maria Santa Maria RS Brazil Univ Fed Pampa Campus Alegrete Alegrete Brazil

ISBN: (纸本)9781728116440

Nowadays computing platforms expose a significant number of heterogeneous processing units such as multicore processors and accelerators. The task-based programming model has been a de facto standard model for such architectures since its model simplifies programming by unfolding parallelism at runtime based on data-flow dependencies between tasks. Many studies have proposed parallel strategies over heterogeneous platforms with accelerators. However, to the best of our knowledge, no dynamic task-based strategy of the Lattice-Boltzmann Method (LBM) has been proposed to exploit CPU+GPU computing nodes. In this paper, we present a dynamic task-based D3Q19 LBM implementation using three runtime systems for heterogeneous architectures: OmpSs, StarPU, and XKaapi. We detail our implementations and compare performance over two heterogeneous platforms. Experimental results demonstrate that our task-based approach attained up to 8.8 of speedup over an OpenMP parallel loop version.

关键词： Task analysis Runtime Graphics processing units Computational modeling parallel processing Programming Computer architecture

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