The AUTOSAR standard provides support for multicore systems since version 4. However, this AUTOSAR multicore version focuses on inter-core communication with a shared memory approach. In contrast, the paradigm of mess...
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ISBN:
(纸本)9781509060580
The AUTOSAR standard provides support for multicore systems since version 4. However, this AUTOSAR multicore version focuses on inter-core communication with a shared memory approach. In contrast, the paradigm of message-basednetwork-on-chips provides multiples advantages for real-time embedded systems such as automotive electronics including better temporal predictability, fault containment and energy efficiency. In this paper we propose an efficient multicore architecture for AUTOSAR based on time-triggered network-on-chips and dedicated input/output cores. Additionally, a health monitoring service is integrated into the AUTOSAR ECU architecture in order to provide recovery actions in case of failures of the automotive application or the hardware of a specific core in the multiprocessor. The results demonstrate how the operating system overhead decreases considerably when using the defined input/output cores that serve as hardware accelerators for the AUTOSAR software. Also, the reliability of the system is improved significantly due to the implemented health monitoring service.
Conventional wired network-on-Chip (NoC) designs suffer from performance degradation due to multi-hop long-distance communication. To address such a problem, in the past decade, researchers have been focused on invest...
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ISBN:
(纸本)9781665469586
Conventional wired network-on-Chip (NoC) designs suffer from performance degradation due to multi-hop long-distance communication. To address such a problem, in the past decade, researchers have been focused on investigating Wireless NoC (WiNoC), which evolved as a viable solution to mitigate this communication bottleneck by using single-hop long-range wireless links. However, many researchers reported that these interconnects may suffer failure due to the complexity of implementation. Although few works in the literature tackle faults in WiNoC, none of them provides a comprehensive study related to channel access mechanisms in the presence of faults. To till this gap, we propose a fault aware WiNoC architecture. We discuss two types of faults in wireless interconnects, namely, transceiver faults and token controller faults. We provide different faultt-olerant techniques to deal with such faults. The proposed FTWiNoC presents, on average, 17.8% and 8.9% improvement in latency compared to two different fault mitigation strategies in the literature.
High performance computing (HPC) is becoming mandatory for the simulation of complex and realistic neuronal models. The development of such realistic models will allow to discover innovative therapies and to study bra...
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ISBN:
(纸本)9781728116440
High performance computing (HPC) is becoming mandatory for the simulation of complex and realistic neuronal models. The development of such realistic models will allow to discover innovative therapies and to study brain diseases without undertaking invasive experiments that are not always possible. However, the models complexity requires adopting suitable technologies in order to provide results in short times, hopefully in real-time. To address this issue, the authors decided to exploit Graphics processing Units (GPUs) in order to develop a realistic and morphologically detailed Purkinje cell model. This paper describes the simulation of the Purkinje cell activity adopting both single and multi-GPU strategy, together with the exploitation of different NVIDIA architectures. Results shows that the simulation times of 10000 cells is reduced from 13 days and 18 hours to about 2 hours.
Infrastructure as a Service providers use virtualization to abstract their hardware and to create a dynamic data center. Virtualization enables the consolidation of virtual machines as well as the migration of them to...
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ISBN:
(纸本)9780769543284
Infrastructure as a Service providers use virtualization to abstract their hardware and to create a dynamic data center. Virtualization enables the consolidation of virtual machines as well as the migration of them to other hosts during runtime. Each provider has its own strategy to efficiently operate a data center. We present a rule based mapping algorithm for VMs, which is able to automatically adapt the mapping between VMs and physical hosts. It offers an interface where policies can be defined and combined in a generic way. The algorithm performs the initial mapping at request time as well as a remapping during runtime. It deals with policy and infrastructure changes. We extended the open source IaaS solution Eucalyptus and we evaluated it with typical policies: maximizing the compute performance and VM locality to achieve a high performance and minimizing energy consumption. The evaluation was done on state-of-the-art servers in our own data center and by simulations using a workload of the parallel Workload Archive. The results show that our algorithm performs well in dynamic data centers environments.
In this paper, a novel approach to prevent accidental or deliberate data breaches is presented. The proposed approach provides platform, network and offline security. Data is categorized as sensitive or insensitive, a...
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ISBN:
(纸本)9780769543284
In this paper, a novel approach to prevent accidental or deliberate data breaches is presented. The proposed approach provides platform, network and offline security. Data is categorized as sensitive or insensitive, and the corresponding applications are isolated by using virtualization technology. Data theft or accidental loss is prevented by encrypting virtual hard disks and by introducing a multi-lane network architecture. If no connection to a corporate network is available, an offline mode handles data transfer and encryption. Authentication is managed by applying a biometric feature vector in association with a smart card setup. The approach increases security without disrupting the everyday work routines of users. An implementation based on VirtualBox and JavaCard is presented. A performance evaluation of the critical components is provided.
It is estimated that up to 25% of the grain crop ends up being lost in the past-harvest. The correct drying of the beans is one of the measures to contain this loss. As the grain mass is a set of solid and empty space...
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ISBN:
(纸本)9781665469586
It is estimated that up to 25% of the grain crop ends up being lost in the past-harvest. The correct drying of the beans is one of the measures to contain this loss. As the grain mass is a set of solid and empty spaces, its drying could be considered a problem of the coupled open-porous medium. In this paper, a mathematical and computer simulation model was proposed, which describes the convection in a free flow with a porous obstacle applied to the drying of the grain. A computational fluid dynamics scheme was implemented in FORTRAN using Finite Volume to simulate and compute the numerical solutions. The code is parallel implemented using OpenMP and OpenACC programming interfaces. As a result, there was a significant reduction in processing time in both cases. The total simulation time was eight times less liar a multicore architecture (16 physical cores) and 17.3 rimes using a single GPU (Quadro M5000).
From information security point of view embedded devices are the elements of complex systems operating in a potentially hostile environment. Therefore development of embedded devices is a complex task that often requi...
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ISBN:
(纸本)9781467387767
From information security point of view embedded devices are the elements of complex systems operating in a potentially hostile environment. Therefore development of embedded devices is a complex task that often requires expert solutions. The complexity of the task of developing secure embedded devices is caused by various types of threats and attacks that may affect the device, as well as that in practice security of embedded devices is usually considered at the final stage of the development process in the form of adding additional security features. The paper proposes a design technique and its application that will facilitate development of secure and energy efficient embedded devices. The technique organizes the search for the best combinations of security components on the basis of solving an optimization problem. The efficiency of the proposed technique is demonstrated by development of a room perimeter protection system.
The communication talents is a primary concern for designing network-on-Chips (NoCs) since it significantly affects the parallel application performance on a many-core computer system. To reduce the communication late...
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ISBN:
(纸本)9781665414555
The communication talents is a primary concern for designing network-on-Chips (NoCs) since it significantly affects the parallel application performance on a many-core computer system. To reduce the communication latency, we propose all on-chip router that (de)compresses the contents of an incoming packet before completing switch arbitration. The compression router thus has no latency penalty for the compression operation, whereas it shortens a packet length that decreases the network injection-and-ejection lateney. Evaluation results show that the compression router improves 7.7% of the parallel application performance (IS, CG, FT, and TSPI and 49% of the effective network throughput by 1.8 compression ratio on NoC. The drawback is that the router area and its energy consumption per bit increase by 0.12mm(2) and 1.4 times compared to the conventional virtual-channel router.
Data movement between memory subsystem and processor unit is a crippling performance and energy bottleneck for data-intensive applications. Near Memory processing (NMP) is a promising solution to alleviate the data mo...
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ISBN:
(纸本)9781665414555
Data movement between memory subsystem and processor unit is a crippling performance and energy bottleneck for data-intensive applications. Near Memory processing (NMP) is a promising solution to alleviate the data movement bottleneck. The introduction of 3D-stacked memories and more importantly hybrid memory systems enable the long-wished NMP capability. This work explores the feasibility and efficacy of having NMP on the hybrid memory system for a given set of applications. In this paper, we first redefine a set of NMP-centric performance metrics in order to analyze the efficacy of a given processing unit. Leveraging the proposed metrics, we characterize various sets of applications to assess the suitability of a processing unit in terms of performance. Specifically, in this work we motivate the efficiency of NMP subsystems to process memory-intensive applications when 3D-NVM technologies are employed.
Analysis of security risks and calculation of security metrics is an important task for Security Information and Events Management (SIEM) systems. It allows recognizing the current security situation and necessary cou...
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ISBN:
(纸本)9781479927289
Analysis of security risks and calculation of security metrics is an important task for Security Information and Events Management (SIEM) systems. It allows recognizing the current security situation and necessary countermeasures. The paper considers technique for calculation of security metrics on the base of attack graphs and service dependencies. The technique uses several assessment aspects or levels (topological, attack graph level, attacker level, events level and system level) and allows customization according to different parameters of SIEM system operation. We discuss also the application of this technique for the "Olympic Games" case study.
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