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An Anti-forensic Method based on RS Coding and distributed Storage 21st

An Anti-forensic Method Based on RS Coding and Distributed S...

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21st International conference on Algorithms and Architectures for parallel processing (ICA3PP)

作者： Jiang, Xuhang Wang, Yujue Ding, Yong Liang, Hai Wang, Huiyong Li, Zhenyu Guilin Univ Elect Technol Sch Comp Sci & Informat Secur Guangxi Key Lab Cryptog & Informat Secur Guilin Peoples R China Pengcheng Lab Cyberspace Secur Res Ctr Shenzhen Peoples R China Guilin Univ Elect Technol Sch Math & Comp Sci Guilin Peoples R China

ISBN: (纸本)9783030953881;9783030953874

The anti-forensics (AF) technology has become a new field of cybercrime. The problems of existing forensic technologies should be considered from criminals' perspective, so as to make improvement to existing AF technologies. There are two types of AF methods, namely, data hiding and destruction, where most AF tools are primarily based on data hiding. If the data can be intercepted by investigators during the AF process, the remaining data may be destroyed by the criminal, which would make investigators obtain nothing about data information. To address this issue, this paper proposes an AF scheme with multi-device storage based on Reed-Solomon codes by combining data hiding and data destruction. The data is divided into multiple out-of-order data blocks and parity blocks, where these blocks are stored separately in different devices. This method can reduce the storage cost and protect the privacy of data. Even if the data is destroyed, it allows AF investigators to recover the data. Security analysis showed that this AF method can prevent malicious, erroneous or invalid files while acquired and ensure data security in data stolen. Theoretical analysis indicated that this method was difficult for investigators but easy for AFer in files recovery. Experimental results demonstrated that the proposed method is effective and has practical efficiency.

关键词： Anti-forensics Digital forensics Encryption Computer crime distributed storage Erasure coding

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Combining Thread Throttling and Mapping to Optimize the EDP of parallel Applications

Combining Thread Throttling and Mapping to Optimize the EDP ...

引用

euromicro conference on parallel, distributed and network-based processing

作者： Gustavo P. Berned Thiarles S. Medeiros Matheus Serpa Fábio D. Rossi Marcelo C. Luizelli Philippe O. Navaux Antonio Carlos S. Beck Arthur F. Lorenzon Federal University of Pampa - Campus Alegrete Brazil Institute of Informatics - Federal University of Rio Grande do Sul Brazil Science and Technology Farroupilha Federal Institute of Education Brazil

Thread-throttling and mapping strategies have been used together to make better use of hardware resources and improve the energy-delay product (EDP) of high-performance computing (HPC) systems. However, the design space exploration significantly grows with the increasing number of cores in those systems, making the task of finding the ideal number of active threads and allocating strategy a challenging task. On top of that, parallel applications present various patterns, such as irregularity, unbalanced computations, or high rates of communications. Given these considerations, we propose ETTM, an EDPaware thread-throttling and mapping optimization strategy that automatically finds an ideal combination of number of threads and thread mapping strategy. With the execution of eighteen well-known benchmarks on three multicore architectures, we show that EDP can be significantly improved when running applications with the solution found by EETM¹.

关键词： Multicore processing Instruction sets distributed databases Computer architecture Benchmark testing Hardware Space exploration

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Autoencoder-based Gradient Compression for distributed Training 29

Autoencoder-Based Gradient Compression for Distributed Train...

引用

29th European Signal processing conference (EUSIPCO)

作者： Abrahamyan, Lusine Chen, Yiming Bekoulis, Giannis Deligiannis, Nikos Vrije Univ Brussel Dept Elect & Informat Brussels Belgium IMEC Kapeldreef 75 B-3001 Leuven Belgium

ISBN: (纸本)9789082797060

Large-scale distributed training has recently been proposed as a solution to speed-up the training of deep neural networks on huge datasets. distributed training, however, entails high communication rates for gradient exchange among computing nodes and requires expensive high-bandwidth network infrastructure. Various gradient compression methods have been proposed to overcome this limitation, including sparsification, quantization, and entropy encoding of the gradients. However, most existing methods leverage only the intra-node information redundancy, that is, they compress gradients at each node independently. In contrast, we advocate that the gradients across the nodes are correlated and propose a method to leverage this inter-node redundancy to obtain higher compression rates. In this work, we propose the Learned Gradient Compression (LGC) framework to reduce communication rates within a distributed training with the parameter server communication protocol. Our framework leverages an autoencoder to capture the common information in the gradients of the distributed nodes and eliminate the transmission of redundant information. Our experiments show that the proposed approach achieves significantly higher gradient compression ratios than state-of-the-art approaches like DGC and ScaleCom.

关键词： Deep learning data-parallel distributed training gradient compression autoencoders

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On GPU optimizations of stencil codes for highly parallel simulations

On GPU optimizations of stencil codes for highly parallel si...

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euromicro conference on parallel, distributed and network-based processing

作者： Nikolai Pfisterer Marco Berghoff Achim Streit Steinbuch Centre for Computing Karlsruhe Institute of Technology Karlsruhe Germany

Stencil codes are valuable methods to solve partial differential equations of models in a wide range of applications in science and engineering. Graphics processing units (GPUs) provide a highly parallel architecture with fast directly accessible memory that is desirable to run stencil codes. They enable larger and more complex simulations that are solved faster compared to simulating on CPUs. We provide a solution for users to run highly parallel stencil codes on GPUs, that can also be efficiently used on a distributed GPU *** this work, we present an extension to the multi-disciplinary framework NAStJA originally designed to efficiently run stencil codes on the CPUs in current high-performance computing (HPC) systems, to also be able to run on GPUs. We describe different methods to increase the performance of stencil codes on GPUs like a border exchange method which is transparent to the user, as well as a buffer for gradient values that are needed multiple times. We show their performance using the phase-field method as a stencil code *** this GPU extension and optimizations implemented into the NAStJA framework, we can show highly improved performance compared to the CPU implementation, and an efficiency of 92% (weak scaling) for a large-scale example simulation on 64 GPUs on the ForHLR II HPC system.

关键词： Partial differential equations Graphics processing units Clustering algorithms Performance gain parallel architectures Central processing Unit Mathematical model

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Underwater Passive Target Detection Fusion based on distributed Acoustic Sensor network

Underwater Passive Target Detection Fusion Based on Distribu...

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2021 IEEE International conference on Signal processing, Communications and Computing, ICSPCC 2021

作者： Li, Qing Ma, Qiming Science and Technology on Sonar Laboratory Hangzhou Applied Acoustics Research Institute Hangzhou China

ISBN: (纸本)9781665429184

This paper proposes a distributed target fusion detection method based on underwater sensor network, which mainly solves the problem of passive detection of underwater targets. A target detection system based on a distributed underwater sensor network is established, which adopts a parallel distributed information fusion structure with a fusion center. Energy of the received signal is utilized on local nodes to obtain the test statistics. Then the corresponding false discovery rate (FDR) is calculated for each node. The fusion center uses the FDR to control the detection threshold and figure out the global decision, which can realize the adaptive adjustment of the detection threshold of local nodes with different received signal-To-noise ratios. The proposed method is conducive to improving range and probability of underwater passive target detection. © 2021 IEEE.

关键词： Signal to noise ratio

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Local Traffic-based Energy-Efficient Hybrid Switching for On-Chip networks

Local Traffic-Based Energy-Efficient Hybrid Switching for On...

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euromicro conference on parallel, distributed and network-based processing

作者： Yuan He Jinyu Jiao Masaaki Kondo Shenyang University of Technology Liaoning China The University of Tokyo Tokyo Japan RIKEN Center for Computational Science Kobe Japan

Advanced flow control mechanisms employed by modern on-chip networks are the reasons of large energy footprint and long per-hop latency. On the other hand, dated and simpler flow controls such as circuit switching can draw far less power and offer an end-to-end latency analogous to wire delay. In this paper, we present a hybrid flow control mechanism, which mixes both virtual channels and circuit-switching, to provide a latency-competitive and energy-efficient on-chip network design. Contrary to existing hybrid switching designs, our proposal is based on local traffic so that circuits are formed without the knowledge of end-to-end traffic. When compared to on-chip networks with virtual channels, our proposal achieves a very competitive latency per flit, for up to 4% lower, while also dramatically suppressing the energy per flit by up to 18%.

关键词： Wires Switches Control systems Energy efficiency System-on-chip Delays Proposals

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Low-Latency Low-Energy Memory-Cube networks using Dual-Voltage Datapaths

Low-Latency Low-Energy Memory-Cube Networks using Dual-Volta...

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euromicro conference on parallel, distributed and network-based processing

作者： Yoshiya Shikama Ryuta Kawano Hiroki Matsutani Hideharu Amano Yusuke Nagasaka Naoto Fukumoto Michihiro Koibuchi Keio University Japan Advanced Institute of Science and Technology Fujitsu Laboratories Ltd. National Institute of Informatics

Three-dimensional stack memory that provides both high-bandwidth access and large capacity is a promising technology for next-generation computer systems. While a large number of memory cubes increase the aggregate memory capacity, the communication latency and power consumption would become significant due to its low-radix large-diameter packet network. In this context, we propose a memory-cube network called Diagonal Memory network (DMN). A diagonal network topology, its floor layout, and its lightweight router are designed for low-latency and low-voltage memory-read communication. Our evaluation results show that a DMN router decreases 31% of the hardware resources than a conventional virtual-channel router. The DMN router reduces 13% and 67% energy consumption to transit a packet along with the original datapath and bypassing datapath, respectively.

关键词： Low voltage Power demand network topology Memory management Layout Routing Throughput

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PC-BNA: parallel Convolution Binary Neural network Accelerator 24

PC-BNA: Parallel Convolution Binary Neural Network Accelerat...

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24th IEEE International conference on High Performance Computing and Communications, 8th IEEE International conference on Data Science and Systems, 20th IEEE International conference on Smart City and 8th IEEE International conference on Dependability in Sensor, Cloud and Big Data Systems and Application, HPCC/DSS/SmartCity/DependSys 2022

作者： Liu, Haihui Zhang, Yuang Zheng, Xiangwei Yu, Mengxin An, Baoxu Liu, Xiaojie School of Information Science and Engineering Shandong Normal University Shandong Provincial Key Laboratory for Distributed Computer Software Novel Technology Jinan China

ISBN: (纸本)9798350319934

Binary neural network (BNN) is widely used in speech recognition, image processing and other fields to save memory and speed up computing. However, the accuracy of the existing binarization scheme in the realistic dataset is obviously low, and the input layer uses 32-bit floating point to avoid excessive precision loss, which requires additional computing units and increases the computational burden. Therefore, it is very important to improve the input layer, save computing resources and reduce precision loss. In this paper, we propose a parallel convolution binary neural network accelerator architecture (PC-BNA). based on our proposed BNN model, we design an efficient field programmable gate array (FPGA) based accelerator. The input of the first layer is binarized, the traditional binary convolution layer is replaced by a parallel binary convolution, and the network building blocks are improved. The experimental results show that the proposed PC-BNA has higher accuracy and better performance on CIFAR-10. The image recognition accuracy is as high as 91.4%, which is superior to the state-of-art of the BNN accelerator. Compared to the state-of-the-art BNN model, when using the same model size, the use of look-up-table (LUT) saves 9.08%, and the digital signal processor (DSP) saves 27.7%. The results suggest that it is promising for PC-BNA in future high performance mobile artificial intelligence applications. © 2022 IEEE.

关键词： Convolution

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High-Performance parallel Fault Simulation for Multi-Core Systems

High-Performance Parallel Fault Simulation for Multi-Core Sy...

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euromicro conference on parallel, distributed and network-based processing

作者： Masoomeh Karami Mohammad-hashem Haghbayan Masoumeh Ebrahimi Hamid Nejatollahi Hannu Tenhunen Juha Plosila University of Turku Turku Finland Royal Institute of Technology (KTH) Kista Sweden. University of California Irvine CA USA.

Fault simulation is a time-consuming process that requires customized methods and techniques to accelerate it. Multi-threading and Multi-core approaches are two promising techniques that can be exploited to accelerate the fault simulation process by using different parts of the hardware at the same time. However, an efficient parallelization is obtained only by the refinement of software with respect to the hardware platform. In this paper, a parallel multi-thread fault simulation technique is proposed to accelerate the simulation process on multi-core platforms. In this approach, the gate input values are independently assigned to each thread. Each input value carries the information of several parallel simulation processes. This provides a multithread parallel fault simulation environment. The experimental results show that the proposed technique can efficiently use the hardware platform. In a single-core platform, the proposed technique can reduce the time by 25% while in a dual-core increasing the thread approximately halves the execution time.

关键词： Multicore processing Instruction sets Very large scale integration Logic gates Hardware Software Circuit faults

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Characterizing Java Streams in the Wild 26

Characterizing Java Streams in the Wild

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26th International conference on Engineering of Complex Computer Systems (ICECCS)

作者： Rosales, Eduardo Rosa, Andrea Basso, Matteo Villazon, Alex Orellana, Adriana Zenteno, Angel Rivero, Jhon Binder, Walter Univ Svizzera Italiana USI Svizzera Switzerland Univ Privada Boliviana La Paz Bolivia

ISBN: (纸本)9781665401623

Since Java 8, streams ease the development of data transformations using a declarative style based on functional programming. Some recent studies aim at shedding light on how streams are used. However, they consider only small sets of applications and mainly apply static analysis techniques, leaving the large-scale analysis of dynamic metrics focusing on stream processing an open research question. In this paper, we present the first large-scale empirical study on the use of streams in Java. We present a novel dynamic analysis for collecting runtime information and key metrics that enable the fine-grained characterization of sequential and parallel stream processing. We massively apply our dynamic analysis using a fully automated approach, supported by a distributed infrastructure to mine public software projects hosted on GitHub. Our findings advance the understanding of the use of streams, both confirming some of the results of previous studies at a much larger scale, as well as revealing previously unobserved findings in the use of streams.

关键词： Java streams Stream processing Code repositories Empirical studies Large-scale study Characterization Dynamic program analysis GitHub Java Virtual Machine

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