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检索条件"任意字段=Euromicro Conference on Parallel, Distributed and Network-Based Processing"

共 4313 条记录，以下是71-80 订阅

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COSMICA: a novel parallel GPU code for Cosmic Rays propagation in heliosphere

COSMICA: a novel parallel GPU code for Cosmic Rays propagati...

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euromicro conference on parallel, distributed and network-based processing

作者： Giovanni Cavallotto Stefano Della Torre Giuseppe La Vacca Massimo Gervasi Division of Milano-Bicocca ICSC - Centro Nazionale di Ricerca in HPC Big Data and Quantum Computing National Institute for Nuclear Physics (INFN) Department of Physics “Giuseppe Occhialini” University of Milano-Bicocca

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

The complex structure of interplanetary magnetic fields and their variability, due to solar activity, make it necessary to compute the Cosmic Ray (CR) modulation with numerical simulations. COde for a Speedy Monte Carlo (MC) Involving Cuda Architecture (COSMICA) is a MC code, solving backward-in-time the system of Stochastic Differential Equations (SDE) equivalent to the Parker Transport Equation (PTE). The Graphics processing Unit (GPU) parallelization of COSMICA code is a game changer in this field because it reduces the computational time of a standard simulation from the order of hundred of minutes to few of them. Furthermore, the code is capable of distributing the computations on clusters of machines with multiple GPUs, opening the way for scaling. In COSMICA we implemented the synchronous broadcasting of memory access for evolving variable samples, the rounding of virtual particle set numbers, to fulfil the GPU blocks, and the exploitation of shared memory to free registers. Furthermore, we compactify the mathematical computations and pass to the lighter momentum formulation of SDE. The first porting of the code on GPU architecture brings it to a speed-up of 40 X. The successful optimizations bring 1.5X speed-up.

关键词： Technological innovation Codes Systematics Computational modeling Graphics processing units Stochastic processes Computer architecture Optimization Cosmic rays Standards

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A Performance Analysis of Autovectorization on RVV RISC-V Boards

A Performance Analysis of Autovectorization on RVV RISC-V Bo...

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euromicro conference on parallel, distributed and network-based processing

作者： Lorenzo Carpentieri Mohammad VazirPanah Biagio Cosenza Department of Computer Science University of Salerno Italy

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

The RISC-V instruction set architecture has become increasingly popular due to its open source and extensible design, making it a competitive choice in high-performance computing and embedded systems. The RISC-V Vector extension (RVV) empowers RISC-V processors with length-agnostic vectorization capabilities, a critical feature for efficiently handling parallel processing demands across different hardware. Compiler support for autovectorization allows to generate vector instructions automatically without requiring any effort to programmers. Given the limited yet evolving compiler support for RVV, this paper offers an in-depth examination of autovectorization capabilities in GCC and LLVM, for RVV version 0.7 and 1.0. We evaluated the autovectorization performance of LLVM, LLVM-EPI and GCC compilers across 151 loops from the Test Suite for Vectorizing Compilers (TSVC) ans seven real-world applications on the AllWinner D1 and BananaPi-F3 boards, representing RISC-V vector hardware. Our study focuses on quantifying and comparing the level of vectorization each compiler achieves across a diverse range of vectorization patterns and workloads, providing insight into their strengths and limitations with respect to RISC-V RVV. Our findings highlight that the LLVM-19 compiler outperforms GCC-14 in 76 out of 151 loops, and its performance is more sensitive to the selection of vector length. Additionally, tuning the vector Length Multiplier (LMUL) parameter can lead to performance improvements of up to $3 x$, and leveraging knowledge of the vector length can further enhance LMUL optimization in compilers.

关键词： Embedded systems Instruction sets High performance computing parallel processing Vectors Hardware Registers Performance analysis Tuning Optimization

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Programming and Mapping for Mixed Heterogeneous Devices: The Case of Optical Flow

Programming and Mapping for Mixed Heterogeneous Devices: The...

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euromicro conference on parallel, distributed and network-based processing

作者： Sergio Alonso Pascual Arturo Gonzalez-Escribano Departamento de Informática Universidad de Valladolid. ETSII Valladolid Spain

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

Current parallel systems are increasingly heterogeneous, mixing devices of different types and computing capabilities. Exploiting multiple different devices for the same application continues to be a challenge that ranges from technical problems related to synchronizing and communicating diverse devices to problems of load distribution and flexibility to adjust the computation to the platform resources. In this work, we study the problem of using and extending a heterogeneous portability layer to program and adapt HSOpticalFlow to heterogeneous platforms. HSOpticalFlow is a streaming application to estimate the apparent movement of objects in a sequence of images. It is a simple but characteristic example of the structure of applications based on multilevel ILS (Iterative Loop Stencil), also known as multi-grid methods, applied to a sequence of inputs. Starting from the original CUDA reference code, we present a methodology and programming techniques based on the Controller programming model to implement it as a pipeline among multiple devices. We discuss a technique to determine a proper work partition and mapping for a set of devices. This allows for building very efficient parallel solutions, using similar devices or taking advantage of devices with lower computing power, to reduce the load and increase the productivity of more powerful ones. We present the results of an experimental study using several GPUs of different vendors, architectures, and generations, showing that this solution allows combinations of devices to be efficiently exploited to improve performance. Specifically, the results include speedups of 1.91x using two NVIDIA A100 GPUs and 1.21x using one NVIDIA V100 GPU and one AMD WX9100 GPU, which is about $3 x$ slower than the NVIDIA GPU for this application.

关键词： Productivity Performance evaluation Computational modeling Pipelines Graphics processing units Computer architecture Programming Streaming media Optical flow Tuning

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The Design of a Computing Platform Architecture for Collaborative Task processing in Avionics System 7th

The Design of a Computing Platform Architecture for Collabor...

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7th China Aeronautical Science and Technology conference, CASTC 2024

作者： Lu, Chenxin Xie, Jianchun Liu, Zuolong Xi’an Aeronautics Computing Technique Research Institute AVIC Xi’an China Key Laboratory of Science and Technology on Airborne and Missileborne Computer Xi’an China

ISBN: (纸本)9789819797738

With the rapid development and application of the concept of multi-aircraft coordinated operations, there are higher requirements for the performance of airborne computing platforms in processing multi-aircraft coordinated tasks. In this study, we have examined the architecture and computing mode of airborne computing platforms in distributed coordinated application scenarios. We have optimized traditional airborne embedded computer architecture, integrated cloud-edge computing technology and heterogeneous parallel computing technology to enhance the performance of airborne computing platforms. We proposes a multi-level heterogeneous distributed collaborative computing platform architecture. The hardware provides modular computing units, while the software implements distributed collaborative resource management and task management mechanisms, along with a unified high-speed network. Additionally, to meet real-time processing requirements for massive data in coordinated task scenarios, we propose a high-throughput computing mode based on the defined platform architecture to ensure task execution throughput through massively parallel acceleration arrays. By integrating the proposed distributed computing architecture with the high throughput computing model, we have developed an integrated airborne distributed collaborative computing platform. In conclusion, we have conducted an analysis of the application of this platform in typical task scenarios of formation coordinated combat. © Chinese Society of Aeronautics and Astronautics 2025.

关键词： HIgh speed networks

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Application of Various Novel Computer Image processing (CIP) Algorithms in Digital Media Art Images

Application of Various Novel Computer Image Processing (CIP)...

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2025 International conference on Multi-Agent Systems for Collaborative Intelligence, ICMSCI 2025

作者： Du, Xian Shanghai Institute of Visual Arts Shanghai201620 China

ISBN: (纸本)9798331509828

With the continuous development of digital image processing algorithms, its application scenarios have been integrated from the simple research of a single image and a single algorithm to a multi-algorithm fusion analysis paradigm. Therefore, this study proposes a digital media art image analysis framework that combines multiple computer image processing (CIP) algorithms. This breakthrough covers three core architectures: image edge extraction, image style transfer, and image compression. In the image edge extraction module, this study designed an improved edge detection algorithm based on de-noising auto-encoder. This algorithm improves the accuracy of edge detection through multi-directional feature extraction and (I, O)-fuzzy rough set optimization, while maintaining global stability. In the image style transfer module, this study proposed a dual-module network. The network includes a texture translation network and a perceptual loss network, and achieves cross-domain style transfer through a fusion model. At the same time, the algorithm optimizes the perceptual loss function to enhance semantic matching capabilities. In the image compression module, this study uses chaotic systems to construct an optimized measurement matrix. Specifically, through a distributed data parallel training framework, a compression method based on the LPAC gradient sparse algorithm is constructed. By testing the three modules separately, the experimental results confirm the effectiveness of the proposed algorithm. © 2025 IEEE.

关键词： Image compression

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PA-Star2: Fast Optimal Multiple Sequence Alignment for Asymmetric Multicore Processors

PA-Star2: Fast Optimal Multiple Sequence Alignment for Asymm...

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euromicro conference on parallel, distributed and network-based processing

作者： Daniel Sundfeld George Teodoro Alba C. M. A. Melo Faculty of Science & Tech. in Engineering University of Brasilia (UnB) Brasilia Brazil Department of Computer Science Federal University of Minas Gerais (UFMG) Belo Horizonte Brazil Department of Computer Science University of Brasilia (UnB) Brasilia Brazil

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

Multiple Sequence Alignment (MSA) is an important operation in Bioinformatics, used to simultaneously compare 3 or more sequences. The MSA problem was proven NP-Hard, so strategies have been proposed to reduce the search space and solve it in parallel. Recently, asymmetric multicore processors (AMPs) have become popular, with performance and energy-efficient cores, like the P-Cores and E-cores from Intel. However, parallel MSA applications have complex access patterns and adapting them for AMPs can be challenging. In this paper, we propose PA-Star2 1 , an asymmetric-aware strategy based on A-Star, which computes optimal MSAs taking asymmetry into account when distributing the search space among threads. Our experimental results show that the proposed optimizations can reduce considerably the average execution time of PA-Star2 achieving a speedup of up to 7.70×. We also show that the asymmetric-aware strategy can reduce the average execution time for one of the hardest sequences set from the BAliBASE benchmark, when compared to the symmetric counterpart. Finally, we show that our approach is energy-efficient. 1 1PA-Star2 is open source and the code is publicly available at1PA-Star2 is open source and the code is publicly available at https://***/danielsundfeld/astar_msa

关键词： Codes Multicore processing Instruction sets Benchmark testing Search problems Energy efficiency Bioinformatics Optimization

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BrahMap: A scalable and modular map-making framework for the CMB experiments

BrahMap: A scalable and modular map-making framework for the...

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euromicro conference on parallel, distributed and network-based processing

作者： Avinash Anand Giuseppe Puglisi Dipartimento di Fisica Università di Roma Tor Vergata Via della Ricerca Scientifica 1 Roma Italy INFN Sezione di Roma2 Università di Roma Tor Vergata Via della Ricerca Scientifica 1 Roma Italy Dipartimento di Fisica e Astronomia Università degli Studi di Catania Via S. Sofia 64 Catania Italy INAF Osservatorio Astrofisico di Catania Via S.Sofia 78 Catania Italy INFN Sezione di Catania Via S.Sofia 64 Catania Italy

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

The cosmic microwave background (CMB) experiments have reached an era of unprecedented precision and complexity. Aiming to detect the primordial B-mode polarization signal, these experiments will soon be equipped with $10^{4}$ to $10^{5}$ detectors. Consequently, future CMB missions will face the substantial challenge of efficiently processing vast amounts of raw data to produce the initial scientific outputs - the sky maps - within a reasonable time frame and with available computational resources. To address this, we introduce BrahMap, a new map-making framework that will be scalable across both CPU and GPU platforms. Implemented in C++ with a user-friendly Python interface for handling sparse linear systems, BrahMap employs advanced numerical analysis and high-performance computing techniques to maximize the use of super-computing infrastructure. This work features an overview of the BrahMap’s capabilities and preliminary performance scaling results, with application to a generic CMB polarization experiment.

关键词： Numerical analysis Scalability Object oriented modeling Pipelines Graphics processing units Numerical models parallel algorithms Object oriented programming Physics Python

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CNS Lock: Compact NUMA-aware Lock with a Standard Interface

CNS Lock: Compact NUMA-aware Lock with a Standard Interface

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euromicro conference on parallel, distributed and network-based processing

作者： Brahmaiah Gandham Praveen Alapati École Centrale School of Engineering Mahindra University Hyderabad India

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

In recent years, multi-core systems with NonUniform Memory Access (NUMA) architectures are becoming prevalent. Multithreaded applications that execute on NUMA architectures play a pivotal role in getting better performance. The difficulties associated with multi-threaded applications are more pronounced because of compatibility issues with synchronization objects and the underlying NUMA architectures. Locks are fundamental synchronization primitives to avoid data races and achieve high performance in multi-core systems. With the increasing performance demands, locks have been refined and optimized with the architectural features of the NUMA systems. This paper proposes a novel synchronization object, namely CNS Lock (Compact NUMA-aware lock with a Standard interface) for NUMA systems. The CNS lock utilizes a single queue irrespective of the number of NUMA nodes and minimizes the number of atomic operations required for lock acquisition and release by prioritizing threads based on their NUMA node affinity. It considers the current thread’s NUMA node number to get the efficiency of a NUMA-aware design. CNS lock provides a standard interface to facilitate seamless integration into existing applications without knowing the internals. The CNS Lock strategically optimizes lock handovers and minimizes memory latency by employing a unified queue system across NUMA nodes. Our experimental results show that the CNS lock significantly outperforms the state-of-the-art locking mechanisms and makes it one of the essential tools of systems with NUMA architectures for better synchronization.

关键词： Multicore processing Instruction sets Memory architecture Handover Synchronization Spinning Resource management Standards

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quickSparseM: a library for memory- and time-efficient computation on large, sparse matrices with application to omics data

quickSparseM: a library for memory- and time-efficient compu...

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euromicro conference on parallel, distributed and network-based processing

作者： Giacomo Baruzzo Giulia Cesaro Barbara Di Camillo Dept. of Information Engineering University of Padova Padova Italy

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

Omics data have revolutionized molecular biology by introducing large-scale data analysis, pushing the field into the realm of big data and presenting substantial challenges in data storage and analysis. Despite describing distinct aspects of molecular biology, most omics data share common characteristics, such as being representable as large, sparse matrices, and requiring similar computational approaches, mainly involving embarrassing parallel tasks across rows or columns. While R is a popular choice for omics analysis, it encounters performance bottlenecks when handling large datasets due to its reliance on dense data formats and constraints like 32-bit indexing in some structures. Even when sparse representations are utilized, the inherent limitations of R lead to inefficiencies. Additionally, its lack of native support for shared-memory parallelism prevents it from fully utilizing modern parallel computing architectures. Similarly, many other data-intensive fields that rely on R face similar challenges with large, sparse data requiring fast and memory-efficient row-wise and column-wise operations. To address these challenges, we introduce quickSparseM, a time- and memory-efficient library for storing and processing large, sparse matrices, available as an R package. Developed in C++ with OpenMP for parallelism, quickSparseM achieves efficient performance while remaining compatible with existing R-based workflows. The library utilizes the R dgCMatrix format to represent sparse matrices in a compressed, column-oriented format and provide functions to compute basic statistics and operations commonly used in omics analyses. Experiments varying dataset sizes and core counts, as well as two case studies using omics data, demonstrate the library’s efficiency and scalability. The results indicate that quickSparseM outperforms state-of-the-art R packages for sparse matrix computation in terms of time, memory usage, and scalability.

关键词： Data analysis Codes Sparse approximation Scalability parallel processing Libraries Software Computational efficiency Sparse matrices Molecular biology

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Boosting Performance of Iterative Applications on GPUs: Kernel Batching with CUDA Graphs

Boosting Performance of Iterative Applications on GPUs: Kern...

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euromicro conference on parallel, distributed and network-based processing

作者： Jonah Ekelund Stefano Markidis Ivy Peng KTH Royal Institute of Technology Sweden

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

Graphics processing Units (GPUs) have become the standard in accelerating scientific applications on heterogeneous systems. However, as GPUs are getting faster, one potential performance bottleneck with GPU-accelerated applications is the overhead from launching several fine-grained kernels. CUDA Graph addresses these performance challenges by enabling a graph-based execution model that captures operations as nodes and dependence as edges in a static graph. Thereby consolidating several kernel launches into one graph launch. We propose a performance optimization strategy for iteratively launched kernels. By grouping kernel launches into iteration batches and then unrolling these batches into a CUDA Graph, iterative applications can benefit from CUDA Graph for performance boosting. We analyze the performance gain and overhead from this approach by designing a skeleton application. The skeleton application also serves as a generalized example of converting an iterative solver to CUDA Graph, and for deriving a performance model. Using the skeleton application, we show that when unrolling iteration batches for a given platform, there is an optimal size of the iteration batch, which is independent of workload, balancing the extra overhead from graph creation with the performance gain of the graph execution. Depending on workload, we show that the optimal iteration batch size gives more than $1.4 \times$ speed-up in the skeleton application. Furthermore, we show that similar speed-up can be gained in Hotspot and Hotspot3D from the Rodinia benchmark suite and a Finite-Difference Time-Domain (FDTD) Maxwell solver.

关键词： Graphics processing units Performance gain Boosting Skeleton Iterative methods Kernel Time-domain analysis Optimization Standards Finite difference methods

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