This paper presents the power consumption estimation for the novel Virtex architecture. Due to the fact that the XC4000 and the Virtex core architecture are very similar, we used the basic approaches for the XC4000-FP...
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This paper presents the power consumption estimation for the novel Virtex architecture. Due to the fact that the XC4000 and the Virtex core architecture are very similar, we used the basic approaches for the XC4000-fpgas power consumption estimation and extended that method for the new Virtex family. We determined an appropriate technology-dependent power factor Kp to calculate the power consumption on Virtex-chips, and developed a special benchmark test design to conduct our investigations. Additionally, the derived formulas are evaluated on two typical industrial designs. Our own emulation environments called SPYDER-ASIC-X1 and SPYDER-VIRTEX-X2 were used, which are best suited for the emulation of hardware designs for embedded systems.
In this paper, we present and analyze a sophisticated communication architecture that allows to integrate many different modules into a system by fpga reconfiguration at runtime. Furthermore, we examine how this archi...
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ISBN:
(纸本)9781605584102
In this paper, we present and analyze a sophisticated communication architecture that allows to integrate many different modules into a system by fpga reconfiguration at runtime. Furthermore, we examine how this architecture can be implemented on low-cost Spartan-3 devices. It will be demonstrated that modules can be exchanged in a system without disturbing the communication architecture. The paper points out, that the capabilities of Spartan-3 fpgas are sufficient to build complex reconfigurable systems. Copyright 2009 acm.
Multitude of design freedoms of LDPC codes and practical decoders require fast simulations. fpga emulation is attractive but inaccessible due to its design complexity. We propose a library and script based approach to...
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ISBN:
(纸本)9781450311557
Multitude of design freedoms of LDPC codes and practical decoders require fast simulations. fpga emulation is attractive but inaccessible due to its design complexity. We propose a library and script based approach to automate the construction of fpga emulations. Code parameters and design parameters are programmed either during run time or by script in design time. We demonstrate the architecture and design flow using the LDPC codes for the latest wireless communication standards: each emulation model was auto-constructed within one minute and the peak emulation throughput reached 3.8 Gb/s on a BEE3 platform.
We present an analytical model relating fpga architectural parameters to the routability of the fpga. The inputs to the model include the channel width and connection and switch block flexibilities, and the output is ...
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ISBN:
(纸本)9781450305549
We present an analytical model relating fpga architectural parameters to the routability of the fpga. The inputs to the model include the channel width and connection and switch block flexibilities, and the output is an estimate of the proportion of nets in a large circuit that can be expected to be routed on the fpga. We assume that the circuit is routed to the fpga using a single-step combined global/detailed router. Together with the earlier works on analytical modeling, our model can be used to predict the routability without going through an expensive CAD flow. We show that the model correctly predicts routability trends.
This paper describes an analytical model that relates the architectural parameters of an fpga to the average prerouting wirelength of an fpga implementation. Both homogeneous and heterogeneous fpgas are considered. Fo...
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ISBN:
(纸本)9781605584102
This paper describes an analytical model that relates the architectural parameters of an fpga to the average prerouting wirelength of an fpga implementation. Both homogeneous and heterogeneous fpgas are considered. For homogeneous fpgas, the model relates the lookup-table size, the cluster size, and the number of inputs per cluster to the expected wirelength. For heterogeneous fpgas, the number and positioning of the embedded blocks, as well as the number of pins on each embedded block is considered. Two applications of the model to fpga architectural design are also presented. Copyright 2009 acm.
fpga bitstream encryption blocks theft of the design in the fpga bitstream by preventing unauthorized copy and reverse engineering. By itself, encryption does not protect against tampering with the bitstream, so witho...
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ISBN:
(纸本)9781450305549
fpga bitstream encryption blocks theft of the design in the fpga bitstream by preventing unauthorized copy and reverse engineering. By itself, encryption does not protect against tampering with the bitstream, so without additional capabilities, bitstream encryption cannot prevent the fpga from executing an unauthorized bitstream. An unauthorized bitstream might be generated by trial and error to cause the fpga to leak confidential data, including the decrypted bitstream. Strong authentication detects tampering with the bitstream, providing a root of trust that enables applications that require protection of sensitive data in a hostile environment. This paper describes the SHA HMAC-based bitstream authentication algorithm and protocol in Virtex-6 fpgas and shows how they are integrated in the bitstream.
Recently there has been interest in using fpgas as a platform for cycle-accurate performance models. We discuss how the properties of fpgas make them a good platform to achieve a performance improvement over software ...
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ISBN:
(纸本)9781595939340
Recently there has been interest in using fpgas as a platform for cycle-accurate performance models. We discuss how the properties of fpgas make them a good platform to achieve a performance improvement over software models. Some metrics are developed to gain insight into the strengths and weaknesses of different simulation methodologies. This paper introduces A-Ports, a distributed, efficient simulation scheme for creating cycle-accurate performance models on fpgas. Finally, we quantitatively demonstrate an average performance improvement of 19% using A-Ports over other fpga-based simulation schemes.
As device densities increase, testing cost is becoming a larger portion of the overall fpga manufacturing cost. We present an approach to speed up testing fpga interconnect by reconfiguring it during the test. Simple ...
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ISBN:
(纸本)9781581134520
As device densities increase, testing cost is becoming a larger portion of the overall fpga manufacturing cost. We present an approach to speed up testing fpga interconnect by reconfiguring it during the test. Simple additions are made to create feedback shift register structures, which considerably reduce the number of test configurations for the switching matrix interconnect. This new testing architecture reduces switching matrix test time by 66% and the diagnosis time by 72%. The additions are transparent to the users both in terms of speed and functionality.
Latency insensitive communication oers many potential benets for fpga designs, including easier timing closure by enabling automatic pipelining, and easier interfacing with embedded NoCs. However, it is important to u...
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ISBN:
(纸本)9781450326711
Latency insensitive communication oers many potential benets for fpga designs, including easier timing closure by enabling automatic pipelining, and easier interfacing with embedded NoCs. However, it is important to understand the costs and trade-os associated with any new design style. This paper presents optimized implementations of latency insensitive communication building blocks, quanties their overheads in terms of area and frequency, and provides guidance to designers on how to generate high-speed and areae cient latency insensitive systems.
In this paper we study the effect of post-layout pin permutation of designs for fpga devices with non-uniform cell delays. We present a simple, but timing optimal, pin permutation scheme, and report the results of app...
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ISBN:
(纸本)9781595930293
In this paper we study the effect of post-layout pin permutation of designs for fpga devices with non-uniform cell delays. We present a simple, but timing optimal, pin permutation scheme, and report the results of applying the scheme on a set of public logic synthesis benchmark designs that were synthesized and placed by state-of-the-art commercial fpga design tools configured to maximum optimization level. Despite the preceding optimizations, we still observed an average timing improvement of 3.7%. This demonstrates the importance of fully utilizing non-uniform cell delays during design optimizations for modern fpga devices and the still presenting potential of improvement. Copyright 2005 acm.
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