As device densities increase, testing cost is becoming a larger portion of the overall fpga manufacturing cost. We present an approach to speed up testing fpga interconnect by reconfiguring it during the test. Simple ...
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ISBN:
(纸本)9781581134520
As device densities increase, testing cost is becoming a larger portion of the overall fpga manufacturing cost. We present an approach to speed up testing fpga interconnect by reconfiguring it during the test. Simple additions are made to create feedback shift register structures, which considerably reduce the number of test configurations for the switching matrix interconnect. This new testing architecture reduces switching matrix test time by 66% and the diagnosis time by 72%. The additions are transparent to the users both in terms of speed and functionality.
Technology mapping is an important step in the fpga CAD flow in which a network of simple gates is converted into a network of logic blocks. We consider enhancements to a traditional LUTbased mapping algorithm for an ...
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ISBN:
(纸本)9781605584102
Technology mapping is an important step in the fpga CAD flow in which a network of simple gates is converted into a network of logic blocks. We consider enhancements to a traditional LUTbased mapping algorithm for an fpga comprised of logic blocks which implement only a subset of functions of up to k variables- specifically, the logic block is a partial LUT, but it possesses more inputs than typical LUTs. Numerical results are presented to demonstrate the efficacy of our proposed techniques using real circuits mapped to a commercial fpga architecture. Copyright 2009 acm.
This paper examines the tradeoffs between flexibility, area, and power dissipation of programmable clock networks for field-programmablegatearrays (fpga's). The paper begins by describing a parameterized clock n...
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ISBN:
(纸本)1595932925
This paper examines the tradeoffs between flexibility, area, and power dissipation of programmable clock networks for field-programmablegatearrays (fpga's). The paper begins by describing a parameterized clock network model that describes a broad range of programmable clock network architectures. Specifically, the model supports architectures with multiple local and global clock domains and varying amounts of flexibility at various levels of the clock network. Using the model, the architectural parameters that control the flexibility of the clock network are varied to determine the cost of this flexibility in terms of area and power dissipation. From these experiments, the study finds that area and power costs are highest for networks with flexibility close to the logic blocks. Furthermore, it found that clock networks with local clock domains have little overhead and are significantly more efficient than clock networks without local clock domains for applications with multiple clocks. Copyright 2006 acm.
Modern fieldprogrammablegatearrays (fpga) can be programmed with multiple soft-core processors. These solutions can be used for MultiProcessor Systems-on-Chip (MPSoCs) prototyping or even for final implementation. ...
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ISBN:
(纸本)9781605584102
Modern fieldprogrammablegatearrays (fpga) can be programmed with multiple soft-core processors. These solutions can be used for MultiProcessor Systems-on-Chip (MPSoCs) prototyping or even for final implementation. Nevertheless, efficient synchronization is required to guarantee performance in multiprocessing environments with the simple cores that do not support atomic instructions and are normally used in the standard fpga toolchains. In this paper, we introduce two hardware synchronization modules for Xilinx MicroBlaze systems, with local polling or queuing mechanisms for locks and barriers, and present a comparison of these solutions to alternative designs. Copyright 2009 acm.
We consider packing in the commercial fpga context and examine the speed, performance and power trade-offs associated with packing in a state-of-the art fpga - the Xilinx (R) Virtex (TM) -5 fpga. Two aspects of packin...
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ISBN:
(纸本)9781595939340
We consider packing in the commercial fpga context and examine the speed, performance and power trade-offs associated with packing in a state-of-the art fpga - the Xilinx (R) Virtex (TM) -5 fpga. Two aspects of packing are discussed: 1) packing for general logic blocks, and 2) packing for large IP blocks. Virtex-5 logic blocks contain dual-output 6-input look-up-tables (LUTs). Such LUTs call implement any single logic function requiring no more than 6 inputs, or any two logic functions requiring no more than 5 distinct inputs. The second LUT Output is associated with slower speed, and therefore, must be used judiciously. We present placement-based techniques for dual-output LUT packing that;lead to improved area-efficiency and power, with minimal performance degradation. We then move on to address packing for large IP blocks, specifically, block RAMs and DSPs. We present a packing optimization that is widely applicable in DSP designs that leads to significantly improved design performance.
A novel Digital to Analog Converter (DAC) modulates the overall power consumption of an fpga by disabling/enabling short circuits programmed into the interconnect. The power pin of the fpga serves as the output of the...
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ISBN:
(纸本)9781450326711
A novel Digital to Analog Converter (DAC) modulates the overall power consumption of an fpga by disabling/enabling short circuits programmed into the interconnect. The power pin of the fpga serves as the output of the DAC. The DAC achieves high linearity and can be used to implement applications in communications, security, etc. The shortcircuit-based DAC consumes 1/3 the area of an alternative shift-register-based DAC that is presented for the sake of comparison.
The aim of this paper is to propose a real time reconfigurable (RTR) micro-fpga using new non volatile memory. Magnetic tunneling junctions (MTJ) used in Magnetic random access memories (MRAM.) are compatible with cla...
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ISBN:
(纸本)1595932925
The aim of this paper is to propose a real time reconfigurable (RTR) micro-fpga using new non volatile memory. Magnetic tunneling junctions (MTJ) used in Magnetic random access memories (MRAM.) are compatible with classical CMOS processes. Moreover remanent property of such a memory could limit configuration time and power consumption required at each power up of the die. Nevertheless, each configuration memory point has to be readable independently from each other, that is why the approach is different from the classical memory array one. Copyright 2006 acm.
Latency insensitive communication oers many potential benets for fpga designs, including easier timing closure by enabling automatic pipelining, and easier interfacing with embedded NoCs. However, it is important to u...
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ISBN:
(纸本)9781450326711
Latency insensitive communication oers many potential benets for fpga designs, including easier timing closure by enabling automatic pipelining, and easier interfacing with embedded NoCs. However, it is important to understand the costs and trade-os associated with any new design style. This paper presents optimized implementations of latency insensitive communication building blocks, quanties their overheads in terms of area and frequency, and provides guidance to designers on how to generate high-speed and areae cient latency insensitive systems.
We are proposing a shared-memory communication infrastructure that provides a common parallel programming interface for fpga and CPU components in a heterogeneous system. Our intent is to ease the integration of recon...
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