检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,335 篇 会议
41 篇 期刊文献

馆藏范围

1,376 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

811 篇 工学
- 784 篇 计算机科学与技术...
- 348 篇 软件工程
- 281 篇 电气工程
- 259 篇 电子科学与技术（可...
- 122 篇 信息与通信工程
- 36 篇 动力工程及工程热...
- 35 篇 控制科学与工程
- 30 篇 机械工程
- 17 篇 生物工程
- 14 篇 仪器科学与技术
- 12 篇 建筑学
- 12 篇 土木工程
- 10 篇 生物医学工程（可授...
- 9 篇 冶金工程
- 8 篇 化学工程与技术
- 7 篇 光学工程
- 7 篇 材料科学与工程（可...
- 3 篇 农业工程
224 篇 理学
- 184 篇 数学
- 36 篇 物理学
- 20 篇 统计学（可授理学、...
- 19 篇 生物学
- 11 篇 系统科学
- 7 篇 化学
62 篇 管理学
- 50 篇 管理科学与工程(可...
- 34 篇 工商管理
- 13 篇 图书情报与档案管...
16 篇 经济学
- 16 篇 应用经济学
11 篇 法学
- 9 篇 社会学
3 篇 农学
- 3 篇 作物学
2 篇 教育学
1 篇 医学

主题

451 篇 fpga
269 篇 field programmab...
171 篇 field programmab...
27 篇 high-level synth...
26 篇 reconfigurable c...
22 篇 deep learning
22 篇 opencl
20 篇 computer archite...
18 篇 hls
18 篇 routing
18 篇 hardware acceler...
18 篇 hardware
17 篇 fpgas
16 篇 accelerator
16 篇 placement
14 篇 neural networks
14 篇 cnn
14 篇 machine learning
14 篇 convolutional ne...
13 篇 clocks

机构

19 篇 university of ca...
12 篇 tsinghua univers...
12 篇 fudan university
12 篇 imperial college...
11 篇 university of to...
10 篇 peking universit...
10 篇 university of to...
9 篇 university of ce...
9 篇 university of so...
8 篇 univ of californ...
7 篇 university of sc...
7 篇 univ of toronto ...
7 篇 epfl lausanne
7 篇 école polytechni...
7 篇 univ toronto dep...
7 篇 nanyang technolo...
7 篇 tsinghua univ pe...
6 篇 univ british col...
6 篇 univ calif los a...
6 篇 northeastern uni...

作者

37 篇 cong jason
26 篇 rose jonathan
22 篇 jason cong
17 篇 betz vaughn
15 篇 zhang zhiru
14 篇 chen deming
13 篇 ienne paolo
12 篇 chow paul
12 篇 wawrzynek john
11 篇 hauck scott
10 篇 dehon andré
10 篇 luk wayne
10 篇 prasanna viktor ...
10 篇 langhammer marti...
9 篇 jinmei lai
9 篇 anderson jason h...
9 篇 wilton steven j....
9 篇 schmit herman
9 篇 jonathan rose
9 篇 constantinides g...

语言

1,356 篇 英文
19 篇 其他
1 篇 中文

检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是131-140 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

A novel fpga logic block for improved arithmetic performance 08

A novel FPGA logic block for improved arithmetic performance

引用

16th acm/sigda international symposium on field-programmable gate arrays, fpga 2008

作者： Parandeh-Afshar, Hadi Brisk, Philip Ienne, Paolo School of Computer and Communication Sciences CH-1015 Lausanne Switzerland

ISBN: (纸本)9781595939340

To improve fpga performance for arithmetic circuits, this paper proposes a new architecture for fpga logic cells that includes a 6:2 compressor. The new cell features additional fast carry-chains that concatenate adjacent compressors and can be routed locally without the global routing network. Unlike previous carry-chains for binary and ternary addition, the carry chain used by the new cell only spans 2 logic blocks, which significantly improves the delay of multi-input addition operations mapped onto the fpga. The delay and area overhead that arises from augmenting a traditional fpga logic cell with the new compressor structure is minimal. Using this new cell, we observed an average speedup in combinational delay of 1.41 compared to adder trees synthesized using ternary adders. Copyright 2008 acm.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

Build Your Own Domain-specific Solutions with RapidWright Invited Tutorial 19

Build Your Own Domain-specific Solutions with RapidWright In...

引用

acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Lavin, Chris Kaviani, Alireza Xilinx Res Labs San Jose CA 95124 USA

ISBN: (纸本)9781450361378

As the complexity of programmable architectures increases with advances in silicon process technology, there is a growing need to extract greater productivity and performance from the tools. Due to their inherent reconfigurability, fpgas are proving to be valuable targets for more efficient domain-specific architectures. However, fpga implementation tools are designed for a broad set of applications. In this paper we describe RapidWright, an open source framework that enables customized implementations for Xilinx fpgas. RapidWright enables implementation tools that can take advantage of the great potential of domain-specific attributes-leading to greater productivity and performance. The focus of this paper is to provide an introductory reference of RapidWright and its use cases so that others may be empowered to adapt their implementations to their domain-specific applications.

关键词： Domain-specific Open Source fpga Xilinx Vivado

来源：评论

学校读者我要写书评

暂无评论

Improved Delay Measurement Method in fpga based on Transition Probability 11

Improved Delay Measurement Method in FPGA based on Transitio...

引用

19th Annual acm international symposium on field-programmable gate arrays

作者： Wong, Justin S. J. Cheung, Peter Y. K. Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn London England

ISBN: (纸本)9781450305549

The ability to measure delay of arbitrary circuits on fpga offers many opportunities for on-chip characterisation and optimisation. This paper describes an improved delay measurement method by monitoring the transition probability at. the output nodes as the operating frequency is swept. The new method uses optimised test vector generation to improve the accuracy of the test method. It is effectively demonstrated on a 4th order IIR filter circuit implemented on an Altera Cyclone III fpga.

关键词： fpga Transition Probability Timing Self Test

来源：评论

学校读者我要写书评

暂无评论

Synthesis for fpgas with embedded memory blocks 00

Synthesis for FPGAs with embedded memory blocks

引用

fpga 2000: acm/sigda international symposium on field programmable gate arrays

作者： Cong, Jason Yan, Kenneth Univ of California Los Angeles CA United States

ISBN: (纸本)9781581131932

Embedded memory blocks (EMBs) are used in modern field programmable gate arrays (fpgas) for implementation of on-chip memories or specialized logic functions. In this paper, we propose an integrated approach with structural clustering and functional decomposition to minimize the circuit area using EMBs while preserving the circuit delay. The structural clustering method is based on the concepts of Maximum Fanout Free Cone (MFFC) and Maximum Fanout Free Subgraph (MFFS). In order to effectively use EMB in large clusters, single-output and multiple-output functional decompositions are used to decompose large clusters so that the encoding functions or base functions can be implemented by EMBs. It also considers multiple EMBs for individual large cluster so that better area reduction can be obtained. We have developed an algorithm called EMB_Syn that can be used as a postprocessing tool in the fpga synthesis flow. MCNC benchmarks are used to test EMB_Syn on Altera's FLEX10K device family and the experimental results are compared with those by EMB_Pack and SMAP. When EMB_Syn is used as postmapping processing, it shows 45.06% and up to 5.23% improvements over EMB_Pack and SMAP, respectively, in terms of the covered area by EMBs.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Representation for dynamic graphs in reconfigurable hardware and its application to fundamental graph algorithms

Representation for dynamic graphs in reconfigurable hardware...

引用

fpga 2000: acm/sigda international symposium on field programmable gate arrays

作者： Huelsbergen, Lorenz Bell Lab Murray Hill United States

This paper gives a representation for graph data structures as electronic circuits in reconfigurable hardware. Graph properties, such as vertex reachability, are computed quickly by exploiting a graph's edge parallelism - signals propagate along many graph edges concurrently. This new representation admits arbitrary graphs in which vertices/edges may be inserted and deleted dynamically at low cost - graph modification does not entail any re-fitting of the graph's circuit. Dynamic modification is achieved by rewriting cells in a re-configurable hardware array. Dynamic graph algorithms are given for vertex reachability, transitive closure, shortest unit path, cycle detection, and connected-component identification. On the task of computing a graph's transitive closure, for example, simulation of such a dynamic graph processor indicates possible speedups greater than three orders of magnitude compared to an efficient software algorithm running on a contemporaneously fast uniprocessor. Implementation of a prototype in an fpga verifies the accuracy of the simulation and demonstrates that a practical and efficient (compact) mapping of the graph construction is possible in existing fpga architectures. In addition to speeding conventional graph computations with dynamic graph processors, we note their potential as parallel graph reducers implementing general (Turing equivalent) computation.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

fpga-Accelerated 3D Reconstruction Using Compressive Sensing 12

FPGA-Accelerated 3D Reconstruction Using Compressive Sensing

引用

20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Chen, Jianwen Cong, Jason Yan, Ming Zou, Yi Univ Calif Los Angeles Dept Comp Sci Los Angeles CA 90095 USA

ISBN: (纸本)9781450311557

The radiation dose associated with computerized tomography (CT) is significant. Optimization-based iterative reconstruction approaches, e.g., compressive sensing provide ways to reduce the radiation exposure, without sacrificing image quality. However, the computational requirement such algorithms is much higher than that of the conventional Filtered Back Projection (FBP) reconstruction algorithm. This paper describes an fpga implementation of one important iterative kernel called EM, which is the major computation kernel of a recent EM+TV reconstruction algorithm. We show that a hybrid approach (CPU+GPU+fpga) can deliver a better performance and energy efficiency than GPU-only solutions, providing 13X boost of throughput than a dual-core CPU implementation.

关键词： image reconstruction fpga CT 3D

来源：评论

学校读者我要写书评

暂无评论

fpga Side-Channel Receivers 11

FPGA Side-Channel Receivers

引用

19th Annual acm international symposium on field-programmable gate arrays

作者： Sun, Ji Bittner, Ray Eguro, Ken Univ Alberta Edmonton AB Canada

ISBN: (纸本)9781450305549

The popularity of fpgas is rapidly growing due to the unique advantages that they offer. However, their distinctive features also raise new questions concerning the security and communication capabilities of an fpga-based hardware platform. In this paper, we explore some of the limits of fpga side-channel communication. Specifically, we identify a previously unexplored capability that significantly increases both the potential benefits and risks associated with side-channel communication on an fpga: an in-device receiver. We designed and implemented three new communication mechanisms: speed modulation, timing modulation and pin hijacking. These non-traditional interfacing techniques have the potential to provide reliable communication with an estimated maximum bandwidth of 3.3 bit/sec, 8 Kbits/sec, and 3.4 Mbits/sec, respectively.

关键词： fpga side-channel receiver thermal phase shift DDR2 I2C

来源：评论

学校读者我要写书评

暂无评论

Scheduling designs into a time-multiplexed fpga 98

Scheduling designs into a time-multiplexed FPGA

引用

Proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, fpga

作者： Trimberger, Steve Xilinx Inc San Jose CA United States

ISBN: (纸本)9780897919784

An algorithm is presented for partitioning a design in time. The algorithm divides a large, technology-mapped design into multiple configurations of a time-multiplexed fpga. These configurations are rapidly executed in the fpga to emulate the large design. The tool includes facilities for optimizing the partitioning to improve routability, for fitting the design into more configurations than the depth of the critical path and for compressing the critical path of the design into fewer configurations, both to fit the design into the device and to improve performance. Scheduling results are shown for mapping designs into an 8-configuration time-multiplexed fpga and for architecture investigation for a time-multiplexed fpga.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

A 2005 review of fpga arithmetic

A 2005 review of FPGA arithmetic

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - fpga 2005

作者： Simard, Stéphane Beguenane, Rachid Larouche, Éric Morin, Luc ERMETIS Research Group Université du Québec à Chicoutimi Chicoutimi Que. G7H 2B1 Canada Novakod Technologies Inc. 930 Jacques Cartier Est Chicoutimi Que. G7H 7K9 Canada

This article is a concise literature review of the actual state of the art in arithmetic for field-programmable gate arrays (fpgas), including studies, implementation techniques, operators, and structures, in various area-time tradeoffs. It covers the integer operations of addition/subtraction, multiplication, squaring, division, and square root, in parallel, and in both serial modes (least-significant digit first, and online). Many people, including researchers in the field of computer arithmetic, parallel computing, digital signal and image processing, system-on-a-programmable chip (SoPC) designers, and other people with a need to implement special purpose arithmetic circuits on fpgas, might find such a review useful, either as an introduction to the topic, as a knowledge update, or for reference.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

DEEP: An Iterative fpga-based Many-Core Emulation System for Chip Verification and Architecture Research 11

DEEP: An Iterative FPGA-based Many-Core Emulation System for...

引用

19th Annual acm international symposium on field-programmable gate arrays

作者： Ributzka, Juergen Hayashi, Yuhei Gao, Guang R. Chen, Fei Univ Delaware Newark DE 19716 USA

ISBN: (纸本)9781450305549

This paper introduces the Delaware Enhanced Emulation Platform (DEEP) - a fpga-based emulation system for hardware/software co-verification of many-core chip architectures. This platform exhibits the following three characteristics: fast compilation of logic designs, debugging support, and affordability. It is based on a novel iterative emulation methodology for hardware design and verification. We also conducted a logic design and integration of a new architectural feature that provides Full/Empty bit fine-grain synchronization for the IBM Cyclops-64 many-core architecture and evaluated its performance against existing synchronization constructs.

关键词： fpga-based emulation many-core architecture fine-grain synchronization

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共138页 << < 10 11 12 13 14 15 16 17 18 19 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：