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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是151-160 订阅

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Highly pipelined asynchronous fpgas

Highly pipelined asynchronous FPGAs

引用

acm/sigda Twelfth acm international symposium on field-programmable gate arrays - fpga 2004

作者： Teifel, John Manohar, Rajit Computer Systems Laboratory Cornell University Ithaca NY 14853 United States

We present the design of a high-performance, highly pipelined asynchronous fpga. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and show how asynchronous logic can efficiently take advantage of this large amount of pipelining. Our fpga, which does not use a clock to sequence computations, automatically "self-pipelines" its logic without the designer needing to be explicitly aware of all pipelining details. This property makes our fpga ideal for throughput-intensive applications and we require minimal place and route support to achieve good performance. Benchmark circuits taken from both the asynchronous and clocked design communities yield throughputs in the neighborhood of 300-400 MHz in a TSMC 0.25μm process and 500-700 MHz in a TSMC 0.18μm process.

关键词： field programmable gate arrays

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Reconfigurable Convolutional Kernels for Neural Networks on fpgas 19

Reconfigurable Convolutional Kernels for Neural Networks on ...

引用

acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Hardieck, Martin Kumm, Martin Moeller, Konrad Zipf, Peter Univ Kassel Kassel Germany

ISBN: (纸本)9781450361378

Convolutional neural networks (CNNs) gained great success in machine learning applications and much attention was paid to their acceleration on field programmable gate arrays (fpgas). The most demanding computational complexity of CNNs is found in the convolutional layers, which account for 90% of the total operations. The fact that parameters in convolutional layers do not change over a long time interval in weight stationary CNNs allows the use of reconfiguration to reduce the resource requirements. This work proposes several alternative reconfiguration schemes that significantly reduce the complexity of sum-of-products operations. The proposed direct configuration schemes provide the least resource requirements and fast reconfiguration times of 32 clock cycles but require additional memory for the pre-computed configurations. The proposed online reconfiguration scheme uses an online computation of the LUT contents to avoid this memory overhead. Finally, a scheme that duplicates the reconfigurable LUTs is proposed for which the reconfiguration time can be completely hidden in the computation time. Combined with a few online reconfiguration circuits, this provides the same configuration memory and configuration time as a conventional parallel kernel but offers large resource reductions of up to 80% of the LUTs.

关键词： Convolutional Neural Networks fpga runtime reconfiguration

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Dynamic reconfiguration in fpga-based SoC designs

Dynamic reconfiguration in FPGA-based SoC designs

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - fpga 2005

作者： Bartosinski, Roman Daněk, Martin Honzik, Petr Matoušek, Rudolf Inst. of Information Theory and Automatioru Czech Academy of Sciences Pod vodarenskou vezi 4 182 08 Praha 8 Czech Republic

This paper discusses architectural issues arising from the use of dynamic reconfiguration and shows a possible use of dynamic reconfiguration to extend and accelerate a computation performed in system-on-a-chip designs with microprocessors with fixed instruction sets. Further a sample application is discussed that uses a dynamically reconfigurable fpga to implement different floating-point calculations in hardware, reconfigured as required by the execution of the user code. The implementation data for two dynamically reconfigurable platforms available on the market - the Xilinx Virtex2 family fpgas and the Atmel FPSLIC family fpgas - is compared in terms of resource requirements, operating frequency, and power consumption.

关键词： field programmable gate arrays

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Exploration of pipelined fpga interconnect structures

Exploration of pipelined FPGA interconnect structures

引用

acm/sigda Twelfth acm international symposium on field-programmable gate arrays - fpga 2004

作者： Sharma, Akshay Compton, Katherine Ebeling, Carl Hauck, Scott Electrical Engineering University of Washington Seattle WA United States Electrical and Computer Engineering Northwestern University Evanston IL United States Computer Science and Engineering University of Washington Seattle WA United States

In this work, we parameterize and explore the interconnect structure of pipelined fpgas. Specifically, we explore the effects of interconnect register population, length of registered routing track segments, registered 10 terminals of logic units, and the flexibility of the interconnect structure on the performance of a pipelined fpga. Our experiments with the RaPiD architecture identify tradeoffs that must be made while designing the interconnect structure of a pipelined fpga. The post-exploration architecture that we found shows a 19% improvement over RaPiD, while the area overhead incurred in placing and routing benchmarks netlists on the post-exploration architecture is 18%.

关键词： field programmable gate arrays

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Analysis of yield loss due to random photolithographic defects in the interconnect structure of fpgas 05

Analysis of yield loss due to random photolithographic defec...

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - fpga 2005

作者： Campregher, Nicola Cheung, Peter Y. K. Vasilko, Milan Constantinides, George A. Electrical and Electronic Engineering Imperial College London United Kingdom School of Design Engineering and Computing Bournemouth University United Kingdom

ISBN: (纸本)9781595930293

This paper presents an analysis of the potential yield loss in fpga due to random defects in metal layers. A proven yield model is adapted to target the fpga interconnect layers in order to predict the manufacturing yield. Defect parameters from the 2003 SIA roadmap are used to investigate the trend in yield loss due to defects in interconnect layers in the future. It is shown that the low yield predicted for the 45nm technology node and beyond is a cause for concern. The potential impact on yield using two different approaches, namely redundant circuits and fault tolerant design, is also presented. Copyright 2005 acm.

关键词： field programmable gate arrays

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Automated synthesis for asynchronous fpgas 05

Automated synthesis for asynchronous FPGAs

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - fpga 2005

作者： Peng, Song Fang, David Teifel, John Manohar, Rajit Computer Systems Laboratory Cornell University Ithaca NY 14853 United States Advanced Microelectronics Department Sandia National Laboratories United States

ISBN: (纸本)9781595930293

Advanced Microelectronics Department at Sandia National Laboratories. We present an automatic logic synthesis method targeted for high-performance asynchronous fpga (Afpga) architectures. Our method transforms sequential programs as well as high-level descriptions of asynchronous circuits into fine-grain asynchronous process netlists suitable for an Afpga. The resulting circuits are inherently pipelined, and can be physically mapped onto our Afpga with standard partitioning and place-and-route algorithms. For a wide variety of benchmarks, our automatic synthesis method not only yields comparable logic densities and performance to those achieved by hand placement, but also attains a throughput close to the peak performance of the fpga. Copyright 2005 acm.

关键词： field programmable gate arrays

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Faithful single-precision floating-point tangent for fpgas 13

Faithful single-precision floating-point tangent for FPGAs

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2013 acm/sigda international symposium on field programmable gate arrays, fpga 2013

作者： Langhammer, Martin Pasca, Bogdan Altera European Technology Centre High Wycombe United Kingdom

ISBN: (纸本)9781450318877

This paper presents an fpga-specific implementation of the floating-point tangent function. The implementation inputs values in the interval [-π/2,π/2], targets the IEEE-754 single-precision format and has an accuracy of 1 ulp. The proposed work is based on a combination of mathematical identities and properties of the tangent function in floating point. The architecture was designed having the {Stratix-IV} DSP and memory blocks in mind but should map well on any contemporary fpga featuring embedded multiplier and memory blocks. It outperforms generic polynomial approximation targeting the same resource spectrum and provides better resources trade-offs than classical CORDIC-based *** presented work is widely available as being part of the Altera DSP Builder Advanced Blockset. © 2013 acm.

关键词： field programmable gate arrays (fpga)

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Interactive debugging at ip block interfaces in fpgas 21

Interactive debugging at ip block interfaces in fpgas

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2021 acm/sigda international symposium on field-programmable gate arrays, fpga 2021

作者： Merlini, Marco Antonio Poy, Isamu Chow, Paul University of Toronto TorontoON Canada

ISBN: (纸本)9781450382182

Recent developments have shown fpgas to be effective for data centre applications, but debugging support in that environment has not evolved correspondingly. This presents an additional barrier to widespread adoption. This work proposes Debug Governors, a new open-source debugger designed for controllability and interactive debugging that can help to locate issues across multiple fpgas. A Debug Governor can pause, log, drop, and/or inject data into any streaming interface. These operations enable single-stepping, unit testing, and interfacing with software. Hundreds of Debug Governors can fit in a single fpga and, because they are transparent when inactive, can be left "dormant"in production designs. We show how Debug Governors can be used to resolve functional problems on a real fpga, and how they can be extended to memory-mapped protocols. © 2021 acm.

关键词： field programmable gate arrays (fpga)

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Reducing the Cost of Floating-Point Mantissa Alignment and Normalization in fpgas 12

Reducing the Cost of Floating-Point Mantissa Alignment and N...

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20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Moctar, Yehdhih Ould Mohammed George, Nithin Parandeh-Afshar, Hadi Ienne, Paolo Lemieux, Guy G. F. Brisk, Philip Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA

ISBN: (纸本)9781450311557

In floating-point datapaths synthesized on fpgas, the shifters that perform mantissa alignment and normalization consume a disproportionate number of LUTs. Shifters are implemented using several rows of small multiplexers;unfortunately, multiplexer-based logic structures map poorly onto LUTs. fpgas, meanwhile, contain a large number of multiplexers in the programmable routing network;these multiplexer are placed under static control of the fpga's configuration bitstream. In this work, we modify some of the routing multiplexers in the intra-cluster routing network of a CLB in an fpga to implement shifters for floating-point mantissa alignment and normalization;the number of CLBs required for these operations is reduced by 67%. If shifting is not required, the routing multiplexers that have been modified can be configured to operate as normal routing multiplexers, so no functionality is sacrificed. The area overhead incurred by these modifications is small, and there is no need to modify every routing multiplexer in the fpga. Experiments show that there is no negative impact in terms of clock frequency or routability for benchmarks that do not use the dynamic multiplexers.

关键词： field programmable gate Array (fpga) Floating-point Mantissa Alignment Normalization

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Eliminating the Memory Bottleneck: An fpga-based Solution for 3D Reverse Time Migration 11

Eliminating the Memory Bottleneck: An FPGA-based Solution fo...

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19th Annual acm international symposium on field-programmable gate arrays

作者： Fu, Haohuan Clapp, Robert G. Tsinghua Univ Ctr Earth Syst Sci Beijing 100084 Peoples R China

ISBN: (纸本)9781450305549

Memory-related constraints (memory bandwidth, cache size) are nowadays the performance bottleneck of most computational applications. Especially in the scenario of multiple cores, the performance does not scale with the number of cores in many cases. In our work, we present our fpga-based solution for the 3D Reverse Time Migration (RTM) algorithm. As the most computationally demanding imaging algorithm in current oil and gas exploration, RIM involves various computational challenges, such as a high demand for storage size and bandwidth, and a poor cache behavior. Combining optimizations from both the algorithmic and architectural perspectives, our fpga-based solution manages to remove the memory constraints and provide a high performance that can scale well with the amount of computational resources available. Compared with an optimized CPU implementation using two quad-core Intel Nehalem CPUs, our solution achieves 4x speedup on two Virtex-5 fpgas, and 8x speedup on two Virtex-6 fpgas. Our projection demonstrates that the performance will continue to scale with the future increase of fpga capacities.

关键词： field programmable gate arrays (fpga) Reverse Time Migration (RTM)

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