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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是161-170 订阅

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New retiming-based technology mapping algorithm for LUT-based fpgas

New retiming-based technology mapping algorithm for LUT-base...

引用

Proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, fpga

作者： Pan, Peichen Lin, Chih-Chang Clarkson Univ Potsdam United States

In this paper, we present a new retiming-based technology mapping algorithm for look-up table-based field programmable gate arrays. The algorithm is based on a novel iterative procedure for computing all k-cuts of all nodes in a sequential circuit, in the presence of retiming. The algorithm completely avoids flow computation which is the bottleneck of previous algorithms. Due to the fact that k is very small in practice, the procedure for computing all k-cuts is very fast. Experimental results indicate the overall algorithm is very efficient in practice.

关键词： field programmable gate arrays

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fpgas vs. CPUs: Trends in peak floating-point performance

FPGAs vs. CPUs: Trends in peak floating-point performance

引用

acm/sigda Twelfth acm international symposium on field-programmable gate arrays - fpga 2004

作者： Underwood, Keith Sandia National Laboratories MS-1110 PO Box 5800 Albuquerque NM 87185-1110

Moore's Law states that the number of transistors on a device doubles every two years: however, it is often (mis)quoted based on its impact on CPU performance. This important corollary of Moore's Law states that improved clock frequency plus improved architecture yields a doubling of CPU performance every 18 months. This paper examines the impact of Moore's Law on the peak floating-point performance of fpgas. Performance trends for individual operations are analyzed as well as the performance trend of a common instruction mix (multiply accumulate). The important result is that peak fpga floating-point performance is growing significantly faster than peak floating-point performance for a CPU.

关键词： field programmable gate arrays

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A soft error vulnerability analysis framework for xilinx fpgas 14

A soft error vulnerability analysis framework for xilinx FPG...

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2014 acm/sigda international symposium on field programmable gate arrays, fpga 2014

作者： Sari, Aitzan Agiakatsikas, Dimitris Psarakis, Mihalis Department of Informatics University of Piraeus Greece

ISBN: (纸本)9781450326711

Today's SRAM-based fpgas provide a reach set of computing resources which makes them attractive in demanding and critical application domains, such as avionics and space. Unfortunately, their high reliance on SRAM configuration memory arise reliability issues due to the single-event upsets (SEUs). Considering the criticality of these applications, the vulnerability analysis of fpga designs to SEUs becomes essential part of the design flow. In this context, we present an open-source framework for the soft error vulnerability analysis of Xilinx fpga devices. The proposed framework will allow researchers to evaluate their reliability-aware CAD algorithms and estimate the soft error susceptibility of the designs at early stages of the implementation flow for the latest Xilinx architectures.

关键词： field programmable gate arrays (fpga)

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Area and Delay Trade-offs in the Circuit and Architecture Design of fpgas 08

Area and Delay Trade-offs in the Circuit and Architecture De...

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16th acm/sigda international symposium on field-programmable gate arrays

作者： Kuon, Ian Rose, Jonathan Univ Toronto Edward S Rogers Sr Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9781595939340

field-programmable gate arrays (fpgas) are used in a wide range of markets that have differing cost, performance and power Consumption requirements. It would be advantageous if a single device family could serve these varied needs but the economics of catering to this wide distribution of market demands suggest more than one family is appropriate. Consequently, fpga vendors have moved to provide a more diverse set, of families that sit at different points in the area-speed-power design space. In this work, our goal is to understand the circuit and architectural design attributes of an fpga that enable trade-offs between area and speed, and to determine the magnitude of the possible trade-offs. This will be useful for architects seeking to determine the number of device families in a suite of offerings, as well as the changes to make between families. We have found that varying both architecture and transistor sizing of art fpga allows the effective area to change by a factor of 3.6 from largest to smallest and the speed to change by a factor of 2.6 from fastest to slowest. It is interesting to observe that the range of area and delay trade-offs possible by varying only the transistor sizing of a single architecture is larger than the ranges observed in past architectural experiments. In addition to transistor size, we note that LUT size is one of the most useful parameters for trading off area and delay.

关键词： fpga Architecture Optimization

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Using bus-based connections to improve field-programmable gate Array density for implementing datapath circuits 05

Using bus-based connections to improve Field-Programmable Ga...

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - fpga 2005

作者： Ye, Andy Rose, Jonathan Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto 10 King's College Road Toronto Ont. M5S 3G4 Canada

ISBN: (纸本)9781595930293

As the logic capacity of field-programmable gate arrays (fpgas) increases, they are being increasingly used to implement large arithmetic-intensive applications, which often contain a large proportion of datapath circuits. Since datapath circuits usually consist of regularly structured components (called bit-slices) which are connected together by regularly structured signals (called buses), it is possible to utilize datapath regularity in order to achieve significant area savings through fpga architectural innovations. This paper describes such an fpga routing architecture, called the multi-bit routing architecture, which employs bus-based connections in order to exploit datapath regularity. It is experimentally shown that, comparing to conventional fpga routing architectures, the multi-bit routing architecture can achieve 14% routing area reduction for implementing datapath circuits, which represents an overall fpga area savings of 10%. This paper also empirically determines the best values of several important architectural parameters for the new routing architecture including the most area efficient granularity values and the most area efficient proportion of bus-based connections. Copyright 2005 acm.

关键词： field programmable gate arrays

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Design space exploration of L1 data caches for fpga-based multiprocessor systems 15

Design space exploration of L1 data caches for FPGA-based mu...

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acm/sigda international symposium on field-programmable gate arrays, fpga 2015

作者： Matthews, Eric Doyle, Nicholas C. Shannon, Lesley Simon Fraser University 8888 University Drive BurnabyBCV5A 1S6 Canada

ISBN: (纸本)9781450333153

Combining multi-processing with the high level of configurability possible with fpga-based soft-processors, this paper presents a multiprocessing framework based on the MicroBlaze soft-processor that provides multicore support and fully coherent, independently configurable Level 1 Caches with Linux multicore support. This architecture allows for finegrain configurability of the system, allowing for fpga resources to be better optimized for a specific embedded application. We use our framework to explore the L1 Data Cache configuration, developing a metric for efficiency based on resource usage and static application runtime. We find that a Pseudo-Random replacement policy is consistently the more efficient choice for fpga systems.

关键词： field programmable gate arrays (fpga)

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Power modeling and architecture evaluation for fpga with novel circuits for Vdd programmability 05

Power modeling and architecture evaluation for FPGA with nov...

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - fpga 2005

作者： Lin, Yan Li, Fei He, Lei Electrical Engineering Department University of California Los Angeles United States

ISBN: (纸本)9781595930293

Vdd-programmable fpgas have been proposed recently to reduce fpga power, where Vdd levels can be customized for different circuit elements and unused circuit elements can be power-gated. In this paper, we first develop an accurate fpga power model and then design novel Vdd-programmable interconnect switches with minimum number of configuration SRAM cells. Applying our power model to placed and routed benchmark circuits, we evaluate Vddprogrammable fpga architecture using the new switches. The best architecture in our study uses Vdd-programmable logic blocks and Vdd-gateable interconnects. Compared to the baseline architecture similar to the leading commercial architecture, the best architecture reduces the minimal energy-delay product by 44.14% with 48% area overhead and 3% SRAM cell increase. Our evaluation results also show that LUT size 4 always gives the lowest energy consumption while LUT size 7 always leads to the highest performance for all evaluated architectures. Copyright 2005 acm.

关键词： field programmable gate arrays

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Making visible the thermal behaviour of embedded microprocessors on fpgas. A progress report

Making visible the thermal behaviour of embedded microproces...

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acm/sigda Twelfth acm international symposium on field-programmable gate arrays - fpga 2004

作者： Lopez-Buedo, Sergio Boemo, Eduardo Computer Engineering Department School of Engineering Universidad Autonoma de Madrid Spain

This paper shows a method to verifying the thermal status of complex fpga-based circuits like microprocessors. Thus, the designer can evaluate if a particular block is working beyond specifications. The idea is to extract the output frequencies of an array of ring-oscillators previously distributed in the die, taking full advantage of the configuration port capabilities in Xilinx technology. As a result, it is shown that the fpga technology offers the designers of embedded systems the possibility of viewing a detailed thermal map of a circuit at a minimum cost. The verification can be done in actual working conditions;for example with heat sinks and fans attached to the chip, inside the system case, or even in an on-board satellite application. The main results of the work are unthinkable using other alternatives like IR cameras, external sensors, or embedded diodes.

关键词： field programmable gate arrays

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fpgaSort: A High Performance Sorting Architecture Exploiting Run-time Reconfiguration on fpgas for Large Problem Sorting 11

FPGASort: A High Performance Sorting Architecture Exploiting...

引用

19th Annual acm international symposium on field-programmable gate arrays

作者： Koch, Dirk Torresen, Jim Univ Oslo Dept Informat N-0316 Oslo Norway

ISBN: (纸本)9781450305549

This paper analyses different hardware sorting architectures in order to implement a highly scaleable sorter for solving huge problems at high performance up to the GB range in linear time complexity. It will be proven that a combination of a FIFO-based merge sorter and a tree-based merge sorter results in the best performance at low cost. Moreover, we will demonstrate how partial run-time reconfiguration can be used for saving almost half the fpga resources or alternatively for improving the speed. Experiments show a sustainable sorting throughput of 2GB/s for problems fitting into the on-chip fpga memory and 1 GB/s when using external memory. These values surpass the best published results on large problem sorting implementations on fpgas, GPUs, and the Cell processor.

关键词： database fpga partial reconfiguration sorting

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Performance and Yield Enhancement of fpgas with Within-die Variation using Multiple Configurations 07

Performance and Yield Enhancement of FPGAs with Within-die V...

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15th acm/sigda international symposium on field-programmable gate arrays

作者： Matsumoto, Yohei Hioki, Masakazu Kawanami, Takashi Tsutsumi, Toshiyuki Nakagawa, Tadashi Sekigawa, Toshihiro Koike, Hanpei Natl Inst Adv Ind Sci & Technol Electroinformat Grp Nanoelect Res Inst Tsukuba Ibaraki 3058568 Japan

ISBN: (纸本)9781595936004

A new method for improving the timing yield of field-programmable gate array (fpga) devices affected by random within-die variation is proposed. By selection of an appropriate configuration from a set of functionally equivalent configurations such that the critical paths do not share same circuit resources oil the fpga, both the average critical path delay and its standard deviation are reduced substantially under conditions of large random variation. Large within-die variations of device parameters such as transistor threshold voltage are anticipated in future semiconductor technologies, resulting in degradation of parametric yields. Comparing to the previous approach which compensates for such within-die variation by designing circuit placement for cacti chip using variation information measured before, our method does not require the measurement of process variations and execution of design tools for cacti chip. The average critical path delay is reduced by up to 5% assuming 30% (sigma/mu) variation in threshold voltage, with a corresponding 50% decrease in standard deviation.

关键词： fpga Configuration Within-Die Variation Timing Yield

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