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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是291-300 订阅

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Compiling High Throughput Network Processors 12

Compiling High Throughput Network Processors

引用

20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Lavasani, Maysam Dennison, Larry Chiou, Derek Univ Texas Austin Austin TX 78712 USA

ISBN: (纸本)9781450311557

Gorilla is a methodology for generating fpga-based solutions especially well suited for data parallel applications with fine grain irregularity. Irregularity simultaneously destroys performance and increases power consumption on many data parallel processors such as General Purpose Graphical Processor Units (GPGPUs). Gorilla achieves high performance and low power through the use of fpga-tailored parallelizadon techniques and application-specific hardwired accelerators, processing engines, and communication mechanisms. Automatic compilation from a stylized C language and templates that define the hardware structure coupled with the intrinsic flexibility of fpgas provide high performance, low power, and programmability. Gorilla's capabilities are demonstrated through the generation of a family of core-router network processors processing up to 100Gbps (200MPPS for 64B packets) supporting any mix of IPv4, IPv6, and Multi-Protocol Label Switching (MPLS) packets on a single fpga with off-chip IP lookup tables. A 40Gbps version of that network processor was run with an embedded test rig on a Xilinx Virtex-6 fpga, verifying for performance and correctness. Its measured power consumption is comparable to full custom, commercial network processors. In addition, it is demonstrated how Gorilla can be used to generate merged virtual routers, saving fpga resources.

关键词： fpga network processor templates

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High-level design tools for floating point fpgas 15

High-level design tools for floating point FPGAs

引用

acm/sigda international symposium on field-programmable gate arrays, fpga 2015

作者： Singh, Deshanand P. Pasca, Bogdan Czajkowski, Tomasz S. Altera Corporation 150 Bloor Street West TorontoON Canada Altera Corporation Westwood High Wycombe BuckinghamshireHP12 4PU United Kingdom

ISBN: (纸本)9781450333153

This tutorial describes tools for efficiently implementing floating point applications on fpgas. We present both the SDK for OpenCL and DSP Builder Advanced Blockset and show that they can be effectively used to implement many floating point applications. The methods for optimizing application performance are also described. In this tutorial we focus on a few applications, including Fast Fourier transform, matrix multiplication, finite impulse response filter and a Cholesky decomposition. In all cases we show what the tools are capable of achieving, and more importantly how a user can take advantage of the various floating-point centric features that are made available. We also discuss how these tools can automatically use fpga architectural features such as hardened floating-point DSP available on Altera Arria 10 family. © Copyright 2015 acm.

关键词： field programmable gate arrays (fpga)

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On the sensitivity of fpga architectural conclusions to experimental assumptions, tools, and techniques 02

On the sensitivity of FPGA architectural conclusions to expe...

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fpga 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Yan, Andy Cheng, Rebecca Wilton, Steven J.E. Dept. of Elec. and Computer Eng. University of British Columbia Vancouver BC Canada

ISBN: (纸本)9781581134520

Recent years have seen a tremendous increase in the capacities and capabilities of field-programmable gate arrays (fpga's). Much of this dramatic improvement has been the result of changes to the fpgas' internal architectures. New architectural proposals are routinely generated in both academia and industry. For fpga's to continue to grow, it is important that these new architectural ideas are fairly and accurately evaluated, so that those worthy ideas can be included in future chips. Typically, this evaluation is done using experimentation. However, the use of experimentation is dangerous, since it requires making assumptions regarding the tools and architecture of the device in question. If these assumptions are not accurate, the conclusions from the experiments may not be meaningful. In this paper, we investigate the sensitivity of fpga architectural conclusions to experimental variations. To make our study concrete, we evaluate the sensitivity of four previously published and well-known fpga architectural results: lookup-table size, switch block topology, cluster size, and memory size. It is shown that these experiments are significantly affected by the assumptions, tools, and techniques used in the experiments.

关键词： field programmable gate arrays

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GPU-Accelerated High-Level Synthesis for Bitwidth Optimization of fpga Datapaths 16

GPU-Accelerated High-Level Synthesis for Bitwidth Optimizati...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Kapre, Nachiket Ye, Deheng Nanyang Technol Univ Sch Comp Engn Singapore 639798 Singapore

ISBN: (纸本)9781450338561

Bitwidth optimization of fpga datapaths can save hardware resources by choosing the fewest number of bits required for each datapath variable to achieve a desired quality of result. However, it is an NP-hard problem that requires unacceptably long runtimes when using sequential CPU-based heuristics. We show how to parallelize the key steps of bitwidth optimization on the GPU by performing a fast brute-force search over a carefully constrained search space. We develop a high-level synthesis methodology suitable for rapid prototyping of bitwidth-annotated RTL code generation using gcc's GIMPLE backend. For range analysis, we perform parallel evaluation of sub-intervals to provide tighter bounds compared to ordinary interval arithmetic. For bitwidth allocation, we enumerate the different bitwidth combinations in parallel by assigning each combination to a GPU thread. We demonstrate up to 10-1000x speedups for range analysis and 50-200x speedups for bitwidth allocation when comparing NVIDIA K20 GPU implementation to an Intel Core i5-4570 CPU while maintaining identical solution quality across various benchmarks. This allows us to generate tailor-made RTL with minimum bitwidths in hundreds of milliseconds instead of hundreds of minutes when starting from high-level C descriptions of dataflow computations.

关键词： field programmable gate arrays (fpga)

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Fast and scalable packet classification using perfect hash

Fast and scalable packet classification using perfect hash

引用

7th acm sigda international symposium on field-programmable gate arrays, fpga'09

作者： Puš, Viktor Korenek, Jan CESNET z. s. p. o. Zikova 4 160 00 Prague Czech Republic Faculty of Information Technology Brno University of Technology Bozetechova 2 612 66 Brno Czech Republic

ISBN: (纸本)9781605584102

Packet classification is an important operation for applications such as routers, firewalls or intrusion detection systems. Many algorithms and hardware architectures for packet classification have been created, but none of them cancompete with the speed of TCAMs in the worst case. We propose new hardware-based algorithm for packet classification. The solution is based on problem decomposition and is aimed at the highest network speeds. A unique property of the algorithm is the constant time complexity in terms of external memory accesses. The algorithm performs exactly two external memory accesses to classify a packet. Using fpga and one commodity SRAM chip, a throughput of 150 million packets per second can be achieved. This makes throughput of 100 Gbps for the shortest packets. Further performance scaling is possible with more or faster SRAM chips. Copyright 2009 acm.

关键词： field programmable gate arrays (fpga)

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Sensing nanosecond-scale voltage attacks and natural transients in fpgas 13

Sensing nanosecond-scale voltage attacks and natural transie...

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2013 acm/sigda international symposium on field programmable gate arrays, fpga 2013

作者： Zick, Kenneth M. Srivastav, Meeta Zhang, Wei French, Matthew Arlington VA United States Virginia Tech. Blacksburg VA United States University of Virginia Charlottesville VA United States

ISBN: (纸本)9781450318877

Voltage noise not only detracts from reliability and performance, but has been used to attack system security. Most systems are completely unaware of fluctuations occurring on nanosecond time scales. This paper quantifies the threat to fpga-based systems and presents a solution approach. Novel measurements of transients on 28nm fpgas show that extreme activity in the fabric can cause enormous undershoot and overshoot, more than 10× larger than what is allowed by the specification. An existing voltage sensor is evaluated and shown to be insufficient. Lastly, a sensor design using reconfigurable logic is presented;its time-to-digital converter enables sample rates 500× faster than the 28nm Xilinx ADC. This enables quick characterization of transients that would normally go undetected, thereby providing potentially useful data for system optimization and helping to defend against supply voltage attacks. © 2013 acm.

关键词： field programmable gate arrays (fpga)

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Enhancements in UltraScale CLB architecture 15

Enhancements in UltraScale CLB architecture

引用

acm/sigda international symposium on field-programmable gate arrays, fpga 2015

作者： Chandrakar, Shant Gaitonde, Dinesh Bauer, Trevor Xilinx Inc. Hyderabad India Xilinx Inc. San JoseCA United States Xilinx Inc. LongmontCO United States

ISBN: (纸本)9781450333153

Each generation of fpga architecture benefits from optimizations around its technology node and target usage. In this paper, we discuss some of the changes made to the CLB for Xilinx's 20nm UltraScale product family. We motivate those changes and demonstrate better results than previous CLB architectures on a variety of metrics. We show that, in demanding scenarios, logic placed in an UltraScale device requires 16% less wirelength than 7-series. Designs mapped to UltraScale devices also require fewer logic tiles. In this paper, we demonstrate the utilization benefits of the Ultra-Scale CLB attributed to certain CLB enhancements. The enhancements described herein result in an average packing improvement of 3% for the example design suite. We also show that the UltraScale architecture handles aggressive, tighter packing more gracefully than previous generations of fpga. These significant reductions in wirelength and CLB counts translate directly into power, performance and ease-of-use benefits.

关键词： field programmable gate arrays (fpga)

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Architecture issues and solutions for a high-capacity fpga 97

Architecture issues and solutions for a high-capacity FPGA

引用

Proceedings of the 1997 acm 5th international symposium on field-programmable gate arrays, fpga

作者： Trimberger, Steve Duong, Khue Conn, Bob Xilinx Inc San Jose CA United States

High-capacity fpgas pose device architects with a variety of problems. The most obvious of these problems is interconnect capacity. Others include interconnect performance, clock distribution and IO capacity. This pap... 详细信息

ISBN: (纸本)9780897918015

关键词： Parallel processing systems

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A Study of Early Aggregation in Database Query Processing on fpgas 23

A Study of Early Aggregation in Database Query Processing on...

引用

31st acm/sigda international symposium on field programmable gate arrays (fpga)

作者： Moghaddamfar, Mehdi May, Norman Faerber, Christian Lehner, Wolfgang Kumar, Akash SAP SE Walldorf Germany Tech Univ Dresden Dresden Germany Intel Corp Munich Germany

ISBN: (纸本)9781450394178

In database query processing, aggregation is an operator by which data with a common property is grouped and expressed in a summary form. Early aggregation is a popular method for improving the performance of the aggregation operator. In this paper, we study early aggregation algorithms in the context of query processing acceleration in database systems on fpgas. The comparative study leads us to set-associative caches with a low inter-reference recency set (LIRS) replacement policy. They show both great performance and modest implementation complexity compared to some of the most prominent early aggregation algorithms. We also present a novel application-specific architecture for implementing set-associative caches. Benchmarks of our implementation show speedups of up to 3x for end-to-end aggregation compared to a state-of-the-art fpga-based query engine.

关键词： fpga database cache early aggregation aggregation

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Interconnect pipelining in a throughput-intensive fpga architecture 01

Interconnect pipelining in a throughput-intensive FPGA archi...

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (fpga 2001)

作者： Singh, A. Mukherjee, A. Marek-Sadowska, M. Department of Electrical Engineering University of California Santa Barbara CA 93106 United States

ISBN: (纸本)9781581133417

Wave-steering is a new design methodology that realizes high throughput circuits by embedding layout friendly synthesized structures in silicon. In the wave-steering design methodology, circuits inherently utilize latches. Inside the synthesized structures they are used for signal skewing, and on the interconnects to guarantee the correct arrival times at the inputs. Recently, we proposed a novel high-throughput fpga architecture based on the wavesteering design principle to handle throughput-intensive applications. Previously our work was focussed mainly on the Logic Block (LB) design. In this paper we discuss a pipelined interconnect scheme to support the strict timing requirements that is necessitated by the wave-steered design style. We characterize designs that best fit the new architecture and show that as technology scales down towards deep submicron (DSM), this fpga fabric shows an increasing throughput performance.

关键词： field programmable gate arrays

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