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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是291-300 订阅

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Accelerating ncRNA homology search with fpgas 13

Accelerating ncRNA homology search with FPGAs

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2013 acm/sigda international symposium on field programmable gate arrays, fpga 2013

作者： McVicar, Nathaniel Ruzzo, Walter L. Hauck, Scott Department of Electrical Engineering University of Washington Seattle WA 98195 United States Department of Computer Science and Engineering Department of Genome Sciences Fred Hutchinson Cancer Research Center Seattle WA 98109 United States

ISBN: (纸本)9781450318877

Over the last decade, the number of known biologically important non-coding RNAs (ncRNAs) has increased by orders of magnitude. The function performed by a specific ncRNA is partially determined by its structure, defined by which nucleotides of the molecule form pairs. These correlations may span large and variable distances in the linear RNA molecule. Because of these characteristics, algorithms that search for ncRNAs belonging to known families are computationally expensive, often taking many CPU weeks to run. To improve the speed of this search, multiple search algorithms arranged into a series of progressively more stringent filters can be used. In this paper, we present an fpga based implementation of some of these algorithms. This is the first fpga based approach to attempt to accelerate multiple filters used in ncRNA search. The fpga is reconfigured for each filter, resulting in a total system speedup of 25x when compared with a single CPU. © 2013 acm.

关键词： field programmable gate arrays (fpga)

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LEAP Scratchpads: Automatic Memory and Cache Management for Reconfigurable Logic 11

LEAP Scratchpads: Automatic Memory and Cache Management for ...

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19th Annual acm international symposium on field-programmable gate arrays

作者： Adler, Michael Fleming, Kermin E. Parashar, Angshuman Pellauer, Michael Emer, Joel Intel Corp VSSAD Grp Santa Clara CA 95051 USA

ISBN: (纸本)9781450305549

Developers accelerating applications on fpgas or other reconfigurable logic have nothing but raw memory devices in their standard toolkits. Each project typically includes tedious development of single-use memory management. Software developers expect a programming environment to include automatic memory management. Virtual memory provides the illusion of very large arrays and processor caches reduce access latency without explicit programmer instructions. LEAP scratchpads for reconfigurable logic dynamically allocate and manage multiple, independent, memory arrays in a large backing store. Scratchpad accesses are cached automatically in multiple levels, ranging from shared on-board, RAM-based, set-associative caches to private caches stored in fpga RAM blocks. In the LEAP framework, scratchpads share the same interface as on-die RAM blocks and are plug-in replacements. Additional libraries support heap management within a storage set. Like software developers, accelerator authors using scratchpads may focus more on core algorithms and less on memory management.

关键词： fpga memory management caches

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Characterization of Long Wire Data Leakage in Deep Submicron fpgas 19

Characterization of Long Wire Data Leakage in Deep Submicron...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Provelengios, George Ramesh, Chethan Patil, Shivukumar B. Eguro, Ken Tessier, Russell Holcomb, Daniel UMass Amherst Amherst MA 01003 USA Microsoft Res Redmond WA USA

ISBN: (纸本)9781450361378

The simultaneous use of fpgas by multiple tenants has recently been shown to potentially expose sensitive information without the victim's knowledge. For example, neighboring long wires in SRAM-based fpgas have been shown to allow for clandestine data exfiltration. In this work, we explore distinct characteristics of this signal crosstalk that could be used to enhance or prevent information leakage. First, we develop a mechanism to characterize the crosstalk coupling that exists between neighboring wires at the femtosecond scale. Second, we show that it is possible to reverse engineer channel layouts by determining which pairs of routing resources/links in the channel exhibit coupling to each other even if this information is not provided by the fpga vendor. To fully characterize these effects, we examine long wire coupling on different types of wires across three devices implemented in different technology nodes from 65 to 20 nm. We experimentally demonstrate that information leakage is apparent for all three fpga families.

关键词： fpga side channel crosstalk

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Hardware-assisted simulated annealing with application for fast fpga placement

Hardware-assisted simulated annealing with application for f...

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acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Wrighton, Michael G. DeHon, André M. California Institute of Technology Computer Science 256-80 Pasadena CA 91125 United States

To truly exploit fpgas for rapid turn-around development and prototyping, placement times must be reduced to seconds;late-bound, reconfigurable computing applications may demand placement times as short as microseconds. In this paper, we show how a systolic structure can accelerate placement by assigning one processing element to each possible location for an fpga LUT from a design netlist. We demonstrate that our technique approaches the same quality point as traditional simulated annealing as measured by a simple linear wirelength metric. Experimental results look ahead to compare quality against VPR's fast placer when considering the minimum channel width required to route as the primary optimization criteria. Preliminary results from an fpga implementation show the feasibility of accelerating simulated annealing by three orders of magnitude using this approach. This means we can place the largest design in the University of Toronto's "fpga Placement and Routing Challenge" in around 4ms.

关键词： field programmable gate arrays

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Compute-Efficient Neural-Network Acceleration 19

Compute-Efficient Neural-Network Acceleration

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Wu, Ephrem Zhang, Xiaoqian Berman, David Cho, Inkeun Thendean, John Xilinx Inc Silicon Architecture San Jose CA 95124 USA

ISBN: (纸本)9781450361378

To enhance the performance of fpga-based neural-network accelerators, maximizing both operating clock rates and compute efficiency is paramount. Streamlining data movement between memory and compute holds the key to boosting these metrics. To unleash latent performance in fpga-based inference processors, we outline a convolutional neural network accelerator that operates at 92.9% of the peak fpga clock rate. First, we map neural-network operators to a minimalist hardware architecture to simplify data movement between memory and compute. Doing so enables the design to close timing at high clock rates. Second, we describe a schedule that keeps compute utilization high. We apply this architecture to classify MNIST, CIFAR-10, and ImageNet datasets. This design achieves 95.5% compute efficiency with GoogLeNet, whose nested topology makes creating an efficient design especially challenging.

关键词： Convolutional neural networks compute efficiency fpga GoogLeNet image classification reduced precision tensor processing accelerator deep learning reconfigurable architecture

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Prototype and Evaluation of the CoRAM Memory Architecture for fpga-Based Computing 12

Prototype and Evaluation of the CoRAM Memory Architecture fo...

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20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Chung, Eric S. Papamichael, Michael K. Weisz, Gabriel Hoe, James C. Mai, Ken Carnegie Mellon Univ Comp Architecture Lab CALCM Pittsburgh PA 15213 USA

ISBN: (纸本)9781450311557

The CoRAM memory architecture for fpga-based computing augments traditional reconfigurable fabric with a natural and effective way for applications to interact with off-chip memory and I/O. The two central tenets of the CoRAM memory architecture are (1) the deliberate separation of concerns between computation versus data marshalling and (2) the use of a multithreaded software abstraction to replace FSM-based memory control logic. To evaluate the viability of the CoRAM memory architecture, we developed a full RTL implementation of a CoRAM microarchitecture instance that can be synthesized for standard cells or emulated on fpgas. The results of our evaluation show that a soft emulation of the CoRAM memory architecture on current fpgas can be impractical for memory-intensive, large-scale applications due to the high performance and area penalties incurred by the soft mechanisms. The results further show that in an envisioned fpga built with CoRAM in mind, the introduction of hard macro blocks for data distribution can mitigate these inefficiencies-allowing applications to take advantage of the CoRAM memory architecture for ease of programmability and portability while still enjoying performance and efficiency comparable to RTL-level application development on conventional fpgas.

关键词： fpga computing memory architecture

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S2N2: A fpga accelerator for streaming spiking neural networks 21

S2N2: A fpga accelerator for streaming spiking neural networ...

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2021 acm/sigda international symposium on field-programmable gate arrays, fpga 2021

作者： Khodamoradi, Alireza Denolf, Kristof Kastner, Ryan University of California San Diego United States Xilinx Longmont United States

ISBN: (纸本)9781450382182

Spiking Neural Networks (SNNs) are the next generation of Artificial Neural Networks (ANNs) that utilize an event-based representation to perform more efficient computation. Most SNN implementations have a systolic array-based architecture and, by assuming high sparsity in spikes, significantly reduce computing in their designs. This work shows this assumption does not hold for applications with signals of large temporal dimension. We develop a streaming SNN (S2N2) architecture that can support fixed-per-layer axonal and synaptic delays for its network. Our architecture is built upon FINN and thus efficiently utilizes fpga resources. We show how radio frequency processing matches our S2N2 computational model. By not performing tick-batching, a stream of RF samples can efficiently be processed by S2N2, improving the memory utilization by more than three orders of magnitude. © 2021 acm.

关键词： field programmable gate arrays (fpga)

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Efficient utilization of heterogeneous routing resources for fpgas

Efficient utilization of heterogeneous routing resources for...

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - fpga 2005

作者： Rautela, Deepak Katti, Rajendra Department of Electrical and Computer Engineering North Dakota State University Fargo ND 58105

The routing resources available in recent fpga architectures (e.g., Xilinx Virtex-II) are very different from the older generation of fpgas (e.g., Xilinx XC4000). The latest fpga architectures have heterogeneous routing resources which include directly driven wires of different lengths and connectivity. Most of the fpga routing algorithms have been implemented on XC4000 style architectures and not much work has been reported for architectures with directly driven heterogeneous routing resources. Since routing resources in fpgas are fixed, it is very important for the routing algorithms to fully exploit the potential of new routing architectures. fpga routing architectures are usually represented as a routing resource graph (RRG). The construction of RRG to accurately model all the routing resources of current fpga architectures is not a trivial task. In this paper we present a simplified scheme to build the RRG for fpga architectures with heterogeneous routing resources. Using our RRG construction scheme we have built a routability driven detailed fpga router named "Bison". We also present a dynamic weight update based heuristic which we have incorporated into the router, so that efficient utilization of routing resources can be achieved.

关键词： field programmable gate arrays

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Multi-Ported Memories for fpgas via XOR 12

Multi-Ported Memories for FPGAs via XOR

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20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： LaForest, Charles Eric Liu, Ming G. Rapati, Emma Rae Steffan, J. Gregory Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 1A1 Canada

ISBN: (纸本)9781450311557

Multi-ported memories are challenging to implement with fpgas since the block RAMs included in the fabric typically have only two ports. Any design that requires a memory with more than two ports must therefore be built out of logic elements or by combining multiple block RAMs. The recently-proposed Live Value Table (LVT) [8] design provides a significant operating frequency improvement over conventional approaches. In this paper we present an alternative approach based on the XOR operation that provides multi-ported memories that use far less logic but more block RAMs than LVT designs, and are often smaller and faster for memories that are more than 512 entries deep. We show that (i) both designs can exploit multipumping to trade speed for area savings, (ii) that multipumped XOR designs are significantly smaller but moderately slower than their LVT counterparts, and (iii) that both the LVT and XOR approaches are valuable and useful in different situations, depending on the constraints and resource utilization of the enclosing design.

关键词： fpga memory multi-port parallel XOR

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Hyper customized processors for bio-sequence database scanning on fpgas 05

Hyper customized processors for bio-sequence database scanni...

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - fpga 2005

作者： Oliver, Tim Schmidt, Bertil Maskell, Douglas Centre for High Performance Embedded Systems Nanyang Technological University Singapore Singapore

ISBN: (纸本)9781595930293

Protein sequences with unknown functionality are often compared to a set of known sequences to detect functional similarities. Efficient dynamic-programming algorithms exist for solving this problem, however current solutions still require significant scan times. These scan time requirements are likely to become even more severe due to exponential database growth. In this paper we present a new approach to bio-sequence database scanning using re-configurable fpga-based hardware platforms to gain high performance at low cost. Efficient mappings of the Smith-Waterman algorithm using fine-grained parallel processing elements (PEs) that are tailored towards the parameters of a query have been designed. We use customization opportunities available at run-time to dynamically hyper customize the systolic array to make better use of available resource. Our fpga implementation achieves a speedup of approximately 170 for linear gap penalties and 125 for affine gap penalties as compared to a standard desktop computing platform. We show how hyper-customization at run-time can be used to further improve the performance. Copyright 2005 acm.

关键词： field programmable gate arrays

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