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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是311-320 订阅

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An Energy-Efficient fpga Implementation of an LSTM Network Using Approximate Computing 19

An Energy-Efficient FPGA Implementation of an LSTM Network U...

引用

Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Elham Azari Aykut Dengi Sarma Vrudhula Arizona State University Tempe AZ USA

ISBN: (纸本)9781450361378

Long Short-Term Memory (LSTM) Recurrent Neural network (RNN) is known for its capability in modeling temporal aspects of data and has been shown to produce promising results in sequence learning tasks such as language modeling. However, due to the large number of model parameters and compute-intensive operations, existing fpga implementations of LSTM cells are not sufficiently energy-efficient as they require large area and exhibit high power consumption. This work describes a substantially different hardware implementation of an LSTM which includes several architectural innovations to achieve high throughput and energy-efficiency. This paper includes extensive exploration of the design trade-offs and demonstrates the advantages for one common application - language modeling. Implementation of the design on a Xilinx Zynq XC7Z030 fpga for language modeling shows significant improvements in throughput and energy-efficiency as compared to the state-of-the-art designs. It is worth mentioning that the proposed LSTM hardware architecture is also applicable to other applications that use LSTM as part of the neural network model (e.g., CNN-RNN models) or in whole (e.g., RNN models).

关键词： long short-term memory hardware acceleration fpga recurrent neural network

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HSC-fpga 19

HSC-FPGA

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Ramtin Zand Ronald F. DeMara University of Central Florida ORLANDO FL USA University of Central Florida Orlando FL USA

ISBN: (纸本)9781450361378

The HSC-fpga offers an intriguing feasible architecture for the next generation of configurable fabrics, which allows embracing the advantages of both CMOS and beyond-CMOS technologies without requiring significant modification to the routing structure, programming paradigms, and synthesis tool-chain of the commercial fpgas. In the HSC-fpga, the intrinsic characteristics of magnetic random access memory (MRAM)-look-up table (LUT) circuits are used to implement sequential logic, while combinational logic circuits are implemented by static random access memory (SRAM)-LUTs. Fabric-level simulation results for the developed HSC-fpga show that it can achieve at least 18%, 70%, and 15% reduction in terms of area, standby power, and read power consumption, respectively, for various ISCAS-89 and ITC-99 benchmark circuits compared to conventional SRAM-based fpgas. The power consumption values can be further decreased by the power-gating allowed by the non-volatility feature of MRAM-LUTs. Moreover, the benefits of increased heterogeneity for reconfigurable computing is extended along realizing probabilistic computing paradigms within a fabric, which is enabled by probabilistic spin logic devices. The cooperating strengths of technology-heterogeneity and heterogeneity in computing paradigm in the proposed HSC-fpga are leveraged to develop energy-efficient and reliability-aware training and evaluation circuits for deep belief networks with memristive crossbar arrays and p-bit based probabilistic neurons.

关键词： probabilistic spin logic device mram spintronics p-bit. reconfigurable computing fpga hybrid device technology reconfigurable logic fabrics post-cmos architectures

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Fault Testing a Synthesizable Embedded Processor at gate Level using UltraScale fpga Emulation 19

Fault Testing a Synthesizable Embedded Processor at Gate Lev...

引用

Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Tom J. Mannos Brian Dziki Moslema Sharif Sandia National Laboratories Albuquerque NM USA Department of Defense Fort G. G. Meade MD USA

ISBN: (纸本)9781450361378

While several applications exist to fault-test software at the abstract level, gate-level fault testing has traditionally been limited to injecting faults into small, dedicated circuits, due the computational time required for gate-level simulations and the logic resources (LUTs and registers) required for fpga emulation. In our work, we leverage the extensive resources of the Ultrascale and Ultrascale+ platforms to systematically test faults on all gate-level inputs of an ASIC or fpga implementation of an embedded processor running a user application. Using a configurable, synthesizable saboteur circuit connected using a scan chain and controlled with a state machine, we tested four different types of faults on each logic gate of the LEON3 CPU running an AES 256 application. The entire process took just under two hours, a 7200X speedup from gate-level simulation. Though neither the hardware nor software employed fault mitigation techniques, we were surprised to discover multiple stuck-at-0, stuck-at-1, and delay faults that resulted in total or partial key and plaintext leakage through the communications serial port. Overall, we identified 22 unique faulty behaviors, four of which involve some form of crypto or memory leakage. These occurred in roughly the same proportions in ASIC and fpga netlists of the LEON3, suggesting robustness of the analysis to different implementations. Of the four static fault types tested, delay faults were the most effective at uncovering behaviors of concern.

关键词： embedded processing fpga emulation asic prototyping cryptography fault injection testing

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Efficient fpga Implementation of Conjugate Gradient Methods for Laplacian System using HLS 19

Efficient FPGA Implementation of Conjugate Gradient Methods ...

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Sahithi Rampalli Natasha Sehgal Ishita Bindlish Tanya Tyagi Pawan Kumar International Institute of Information Technology Hyderabad India

ISBN: (纸本)9781450361378

In conjugate gradient method to solve partial differential equations, matrix vector operations are required in each iteration; these matrix vector operations can be implemented as 5 point finite difference stencil operations on the grid without explicitely constructing the matrix. We show that a pipelined and superscalar design using high level synthesis (HLS) leads to a significant reduction in latencies for two variants of conjugate gradient methods considered. When comparing these two, we show that the second method has roughly two times lower latency than the former given the same degree of superscalarity. These reductions in latencies for the newer variant of CG is due to parallel implementations of stencil operation on subdomains of the grid, and due to overlap of these stencil operations with dot product operations. In a superscalar design for the stencil operation, the computational domain needs to be partitioned, and boundary data needs to be copied, which requires padding. We propose a novel traversal of the grid for 2D domain decomposition that leads to reduction in latency cost involved with padding. The fpga implementation of CG is roughly 7 times faster than state-of- the-art sequential implementation, and roughly 4 times faster than state-of-the-art CUDA library parallel implementation for the linear system of dimension 10000 x 10000.

关键词： fpga high level synthesis laplace system pipelining superscalarity conjugate gradient

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JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC fpga Soft-cores 19

JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V ...

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Katie Lim Jonathan Balkind David Wentzlaff University of Washington Seattle WA USA Princeton University Princeton NJ USA Princeton University Princeton NJ USA

ISBN: (纸本)9781450361378

Energy efficiency has become an increasingly important concern in computer architecture due to the end of Dennard scaling. Heterogeneity has been explored as a way to achieve better energy efficiency and heterogeneous microarchitecture chips have become common in the mobile setting. Recent research has explored using heterogeneous-ISA, heterogeneous microarchitecture, general-purpose cores to achieve further energy efficiency gains. However, there is no open-source hardware implementation of a heterogeneous-ISA processor available for research, and effective research on heterogeneous-ISA processors necessitates the emulation speed provided by fpga prototyping. This work describes our experiences creating JuxtaPiton by integrating a small RISC-V core into the OpenPiton framework, which uses a modified OpenSPARC T1 core. This is the first time a new core has been integrated with the OpenPiton framework, and JuxtaPiton is the first open-source, general-purpose, heterogeneous-ISA processor. JuxtaPiton inherits all the capabilities of OpenPiton, including vital fpga emulation infrastructure which can boot full-stack Debian Linux. Using this infrastructure, we investigate area and timing effects of using the new RISC-V core on fpga and the performance of the new core running microbenchmarks.

关键词： energy efficiency heterogeneous multicore shared memory heterogeneous microarchitecture heterogeneous isa manycore

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Rapid Prototyping of Parameterized Rotated and Cyclic Q Delayed Constellations Demapper 29

Rapid Prototyping of Parameterized Rotated and Cyclic Q Dela...

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29th international symposium on Rapid System Prototyping, RSP 2018

作者： Waqas, Muhammad Jafri, Atif Raza Baghdadi, Amer Najam-Ul-Islam, M. Bahria University Islamabad Pakistan Lab-STICC laboratory IMT Atlantique Brest France

ISBN: (纸本)9781538675571

Rotated and Cyclic Q Delayed (RCQD) modulation is one of the signal processing schemes which, once used on the transmitter side, provides performance improvement on receiver side in case of fading channel conditions with erasures. However, an efficient hardware solution in terms of low area and high throughput is mandatory to get benefit from this modulation technique. In this paper we have implemented a parameterized hardware architecture of most recent RCQD demapping technique supporting different constellations. In addition to the description of the proposed hardware architecture, rapid prototyping flow based on LabVIEW fpga is described which is useful to explore different design schemes in short period of time. The implementation results are achieved by fpga prototyping while targeting NI-USRP RIO hardware equipment. By comparing our rapidly prototyped parameterized RCQD demapper with other state-of-the-art implementation schemes, it is shown that our prototyped demapper consumed lesser hardware resources and achieved higher throughput with very short design time. © 2018 IEEE.

关键词： field programmable gate arrays (fpga)

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fpga-based Distributed Edge Training of SVM 19

FPGA-based Distributed Edge Training of SVM

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Jyotikrishna Dass Yashwardhan Narawane Rabi Mahapatra Vivek Sarin Texas A&M University College Station TX USA

ISBN: (纸本)9781450361378

Support Vector Machine (SVM) is a widely used supervised machine learning algorithm for classification. Training SVM is challenging due to high computational cost and memory requirements. More often such training is handled at back end servers leading to significant communication and energy overheads. This approach is unsuitable for edge analytics which is a growing trend with various IoT applications. Enabling efficient training on the edge requires a distributed computing approach that has negligible communication overhead and an energy-efficient hardware design to execute it. In this paper, we present a scalable fpga-based design for distributed SVM training amenable for edge-based learning. Specifically, we implement a pipelined QRSVM IP logic on Xilinx Virtex UltraScale+ VU9P fpga. Each synthesized IP core operates at 125 MHz with a power dissipation of 39 Watts. We evaluate the training time, parallel speedup, scalability, and energy efficiency of the proposed design on five SVM benchmarks on a multiple fpga system comprising up to eight fpga units. When compared with software implementation on the traditional embedded system edge processors like ARM Cortex-A15, the proposed fpga implementation is around 3x to 24x faster and 2x to 8x more energy efficient on the above benchmarks.

关键词： machine learning fpga svm distributed computing qr decomposition

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On Feasibility of fpgas Without Dedicated programmable Interconnect Structure 19

On Feasibility of FPGAs Without Dedicated Programmable Inter...

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Anastasiia Kucherenko Stefan Nikolic Paolo Ienne École Polytechnique Fédérale de Lausanne (EPFL) Lausanne Switzerland

ISBN: (纸本)9781450361378

It is a well known fact that a great majority of fpga chip area goes into the programmable interconnect structure. Since area consumption is mostly proportional to the level of flexibility the interconnect structure offers, how much of this flexibility is really needed for the implementation of any design of interest is a logical question to pose. Going one step further, one may wonder if a dedicated programmable interconnect structure is even necessary. This work answers exactly this second question by providing constructive capability proofs, for a broad class of fpga architectures composed solely of look-up tables (LUTs) connected in a fixed manner, to implement any circuit graph. Our proposed architectures consist of identical cells of LUTs with fixed connections, arranged on a 2D grid. Direct wires between cell input and output pins are also allowed, enabling long uninterrupted connections. We begin by formalizing the above architecture class, and then describe an algorithm capable of mapping any circuit on one specific member of it, in which each cell consists of a single 4-LUT. We derive area and runtime bounds for the algorithm, and finally extend it to be applicable to any architecture in which no LUT receives more than K - 4 inputs from within the cell (K is LUT size) and the number of sink LUTs of the cell does not exceed the number of source LUTs. Presented algorithms serve to answer the posed question, but, due to area-inefficiency, do not have much practical value at this point.

关键词： periodic graphs routing algorithms universality proofs fixed interconnect hard-wired fpgas

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FTConv: fpga Acceleration for Transposed Convolution Layers in Deep Neural Networks 19

FTConv: FPGA Acceleration for Transposed Convolution Layers ...

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Zhucheng Tang Guojie Luo Ming Jiang Peking University Beijing China

ISBN: (纸本)9781450361378

Transposed convolution, which is often used to scale up feature maps in various computer vision tasks, is a structural inverse process of convolution. Both convolution and transposed convolution, if any, account for the majority of computation in the inferences of deep neural networks. While convolution has been studied extensively, there are few investigations on accelerating transposed convolution. In this paper, we propose a fast algorithm, FTConv, to reduce the computation of transposed convolution using the Winograd algorithm, which has also been used for convolution with small kernels. Specifically, a transposed convolution can be converted into multiple convolutions after dividing the kernel into several congruence classes. Thus, we can accelerate the multiple convolutions using a modified Winograd algorithm. The transposed convolution can be obtained by interleaving output feature elements of each congruence class. We also design a Winograd ALU in four pipeline stages to further accelerate the computation on fpga. By carefully designing a sliding window for on-chip buffer reuse according to the memory access pattern of transposed convolution, we save the memory bandwidth by 88.2% compared with a straightforward method. We evaluate FTConv using FSRCNN-s, a neural network for super-resolution. The number of multiplications in the transposed convolution layer can be reduced by 69% over the direct computation of FSRCNN-s.

关键词： transposed convolution winograd algorithm fpga acceleration

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Compressed CNN Training with fpga-based Accelerator 19

Compressed CNN Training with FPGA-based Accelerator

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Kaiyuan Guo Shuang Liang Jincheng Yu Xuefei Ning Wenshuo Li Yu Wang Huazhong Yang Tsinghua University Beijing China

ISBN: (纸本)9781450361378

Training convolutional neural network (CNN) usually requires large amount of computation resource, time and power. Researchers and cloud service providers in this region needs fast and efficient training system. GPU is currently the best candidate for CNN training. But fpgas have already shown good performance and energy efficiency as CNN inference accelerators. In this work, we design a compressed training process together with an fpga-based accelerator for energy efficient CNN training. We adopt two of the widely used model compression methods, quantization and pruning, to accelerate CNN training process. The difference between inference and training brought challenges to apply the two methods in training. First, training requires higher data precision. We use the gradient accumulation buffer to achieve low operation complexity while keeping gradient descent precision. Second, sparse network results in different types of functions in forward and back-propagation phases. We design a novel architecture to utilize both inference and back-propagation sparsity. Experimental results show that the proposed training process achieves similar accuracy compared with traditional training process with floating point data. The proposed accelerator achieves 641GOP/s equivalent performance and 2.86x better energy efficiency compared with GPU.

关键词： training fpga convolutional neural network

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