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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是311-320 订阅

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Boolean Satisfiability-Based Routing and Its Application to Xilinx UltraScale Clock Network 16

Boolean Satisfiability-Based Routing and Its Application to ...

引用

acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Fraisse, Henri Joshi, Abhishek Gaitonde, Dinesh Kaviani, Alireza Xilinx Inc San Jose CA 95124 USA

ISBN: (纸本)9781450338561

Boolean Satisfiability (SAT)-based routing offers a unique advantage over conventional routing algorithms by providing an exhaustive approach to find a solution. Despite that advantage, commercial fpga CAD tools rarely use SAT-based routers due to scalability issues. In this paper, we revisit SAT-based routing and propose two SAT formulations independent of routing architecture. We then demonstrate that SAT-based routing using either formulation dramatically outperforms conventional routing algorithms in both runtime and robustness for the clock routing of Xilinx UltraScale devices. Finally, we experimentally show that one of the proposed SAT formulations leads to a routing 18x faster and produces formulas 20x more compact than the other. This framework has been implemented into Vivado [21] and is now currently used in production.

关键词： Boolean Satisfiability SAT routing clock network fpga

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BiS-KM: Enabling Any-Precision K-Means on fpgas 20

BiS-KM: Enabling Any-Precision K-Means on FPGAs

引用

acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： He, Zhenhao Wang, Zeke Alonso, Gustavo Swiss Fed Inst Technol Dept Comp Sci Syst Grp Zurich Switzerland

ISBN: (纸本)9781450370998

K-Means is a popular clustering algorithm widely used and extensively studied in the literature. In this paper we explore the challenges and opportunities in using low precision input in conjunction with a standard K-Means algorithm as a way to improve the memory bandwidth utilization on hardware accelerators. Low precision input through quantization has become a standard technique in machine learning to reduce computational costs and memory traffic. When applied in fpgas, several issues need to be addressed. First and foremost is the overhead of storing the data at different precision levels since, depending on the training objective, different levels of precision might be needed. Second, the fpga design needs to accommodate varying precision without requiring reconfiguration. To address these concerns, we propose Bit-Serial K-Means (BiS-KM), a combination of a hybrid memory layout supporting data retrieval at any level of precision, a novel fpga design based on bit-serial arithmetic, and a modified K-Means algorithm tailored to fpgas. We have tested BiS-KM with various data sets and compared our design with a state-of-the-art fpga accelerator. BiS-KM achieves an almost linear speedup as precision decreases, providing a more effective way to perform K-Means on fpgas.

关键词： fpga K-Means Bit-Serial Arithmetic Low-Precision Clustering Memory Layout

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A 475 MHz Manycore fpga Accelerator for RTL Simulation 24

A 475 MHz Manycore FPGA Accelerator for RTL Simulation

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32nd acm international symposium on field-programmable gate arrays, fpga 2024

作者： Kashani, Sahand Emami, Mahyar Kamahori, Keisuke Pourghannad, Sepehr Raj, Ritik Larus, James R. Epfl Lausanne Switzerland University of Washington Seattle United States Georgia Tech Atlanta United States

ISBN: (纸本)9798400704185

This paper presents the implementation of Manticore: a manycore accelerator for parallel RTL simulation. Manticore packs up to 225 custom soft processors running at 475 MHz on a large fpga. Implementing manycore accelerators on fpgas is challenging as designers must reconcile the conflicting goals of maximizing the number of cores on the chip and clocking them at the highest possible frequency. Designers face two classes of constraints: (1) architectural constraints imposed by a large fpga's multi-die structure, and (2) physical constraints imposed by the fpga shell's size and placement. Physical design therefore plays a critical role in the implementation of manycore accelerators. We present physical design challenges faced during Manticore's implementation on the AMD Alveo U200 card - -a large fpga with a poorly-placed, wide shell that challenges physical implementation. © 2024 Owner/Author.

关键词： field programmable gate arrays (fpga)

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A compact fpga implementation of the hash function whirlpool 06

A compact FPGA implementation of the hash function whirlpool

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14th acm/sigda international symposium on field programmable gate arrays - fpga 2006

作者： Pramstaller, Norbert Rechberger, Christian Rijmen, Vincent Graz University of Technology Austria

ISBN: (纸本)1595932925

Recent breakthroughs in cryptanalysis of standard hash functions like SHA-1 and MD5 raise the need for alternatives. A credible alternative to for instance SHA-1 or the SHA-2 family of hash functions is Whirlpool. Whirlpool is a hash function that has been evaluated and approved by NESSIE and is standardized by ISO/IEC. To the best of our knowledge only one fpga implementation of Whirlpool has been published to date. This implementation is designed for high throughput rates requiring a considerable amount of hardware resources. In this article we present a compact hardware implementation of the hash function Whirlpool. The proposed architecture uses an innovative state representation that makes it possible to reduce the required hardware resources remarkably. The complete implementation requires 1456 CLB-slices and, most notably, no block RAMs. Copyright 2006 acm.

关键词： Function evaluation

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Accelerating ncRNA homology search with fpgas 13

Accelerating ncRNA homology search with FPGAs

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2013 acm/sigda international symposium on field programmable gate arrays, fpga 2013

作者： McVicar, Nathaniel Ruzzo, Walter L. Hauck, Scott Department of Electrical Engineering University of Washington Seattle WA 98195 United States Department of Computer Science and Engineering Department of Genome Sciences Fred Hutchinson Cancer Research Center Seattle WA 98109 United States

ISBN: (纸本)9781450318877

Over the last decade, the number of known biologically important non-coding RNAs (ncRNAs) has increased by orders of magnitude. The function performed by a specific ncRNA is partially determined by its structure, defined by which nucleotides of the molecule form pairs. These correlations may span large and variable distances in the linear RNA molecule. Because of these characteristics, algorithms that search for ncRNAs belonging to known families are computationally expensive, often taking many CPU weeks to run. To improve the speed of this search, multiple search algorithms arranged into a series of progressively more stringent filters can be used. In this paper, we present an fpga based implementation of some of these algorithms. This is the first fpga based approach to attempt to accelerate multiple filters used in ncRNA search. The fpga is reconfigured for each filter, resulting in a total system speedup of 25x when compared with a single CPU. © 2013 acm.

关键词： field programmable gate arrays (fpga)

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Regularity Matters: Designing Practical fpga Switch-Blocks 23

Regularity Matters: Designing Practical FPGA Switch-Blocks

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31st acm/sigda international symposium on field programmable gate arrays (fpga)

作者： Nikolic, Stefan Ienne, Paolo Ecole Polytech Fed Lausanne EPFL Lausanne Switzerland

ISBN: (纸本)9781450394178

Several techniques have been proposed for automatically searching for fpga switch-blocks which typically show some tangible advantage over the well-known academic architectures. However, the resulting switch-blocks usually exhibit high levels of irregularity, in contrast with what can be observed in a typical commercial architecture. One wonders whether the architectures produced by such search methods can actually be laid out in an efficient manner while retaining the perceived gains. In this work, we propose a new switch-block exploration method that enhances a recently published search algorithm by combining it with ILP, in order to guarantee that the obtained solution satisfies arbitrary regularity constraints. We measure the impact of regularity constraints commonly seen in industrial architectures (such as limiting the number of different multiplexer sizes or forced sharing of inputs between pairs of multiplexers) and observe benefits to the routability of complex circuits with only a limited reduction in performance.

关键词： interconnect routability automated exploration layout regularity multiplexer input sharing constraint ILP optimization avalanche

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A Cycle-accurate, Cycle-reproducible multi-fpga System for Accelerating Multi-core Processor Simulation 12

A Cycle-accurate, Cycle-reproducible multi-FPGA System for A...

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20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Asaad, Sameh Bellofatto, Ralph Brezzo, Bernard Haymes, Chuck Kapur, Mohit Parker, Benjamin Roewer, Thomas Saha, Proshanta Takken, Todd Tierno, Jose IBM TJ Watson Res Ctr Yorktown Hts NY 10598 USA

ISBN: (纸本)9781450311557

Software based tools for simulation are not keeping up with the demands for increased chip and system design complexity. In this paper, we describe a cycle-accurate and cycle-reproducible large-scale fpga platform that is designed from the ground up to accelerate logic verification of the Bluegene/Q compute node ASIC, a multi-processor SOC implemented in IBM's 45 rim SOI CMOS technology. This paper discusses the challenges for constructing such large-scale fpga platforms, including design partitioning, clocking & synchronization, and debugging support, as well as our approach for addressing these challenges without sacrificing cycle accuracy and cycle reproducibility. The resulting fullchip simulation of the Bluegene/Q compute node ASIC runs at a simulated processor clock speed of 4 MHz, over 100,000 times faster than the logic level software simulation of the same design. The vast increase in simulation speed provides a new capability in the design cycle that proved to be instrumental in logic verification as well as early software development and performance validation for Bluegene/Q.

关键词： fpga Multi-core Logic Emulation

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Stochastic, spatial routing for hypergraphs, trees, and meshes

Stochastic, spatial routing for hypergraphs, trees, and mesh...

引用

acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Huang, Randy Wawrzynek, John DeHon, André UC Berkeley Soda Hall 1776 Berkeley CA 94720 United States Dept. of CS 256-80 California Institute Technology Pasadena CA 91125 United States

fpga place and route is time consuming, often serving as the major obstacle inhibiting a fast edit-compile-test loop in prototyping and development and the major obstacle preventing late-bound hardware and design mapping for reconfigurable systems. Previous work showed that hardware-assisted routing can accelerate fanout-free routing on Fat-Trees by three orders of magnitude with modest modifications to the network itself. In this paper, we show how these techniques can be applied to any fpga and how they can be implemented on top of LUT networks in cases where modification of the fpga itself is not justified. We further show how to accommodate fanout and how to achieve comparable route quality to software-based methods. For a tree network, we estimate an fpga implementation of our routing logic could route the Toronto Place and Route Benchmarks at least two orders of magnitude faster than a software Pathfinder while achieving within 3% of the aggregate quality. Preliminary results on small mesh benchmarks achieve within one track of vpr -fast.

关键词： field programmable gate arrays

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Fingerprinting Cloud fpga Infrastructures 20

Fingerprinting Cloud FPGA Infrastructures

引用

acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Tian, Shanquan Xiong, Wenjie Giechaskiel, Ilias Rasmussen, Kasper Szefer, Jakub Yale Univ New Haven CT 06520 USA Univ Oxford Oxford England

ISBN: (纸本)9781450370998

In recent years, multiple public cloud fpga providers have emerged, increasing interest in fpga acceleration of cryptographic, bioinformatic, financial, and machine learning algorithms. To help understand the security of the cloud fpga infrastructures, this paper focuses on a fundamental question of understanding what an adversary can learn about the cloud fpga infrastructure itself, without attacking it or damaging it. In particular, this work explores how unique features of fpgas can be exploited to instantiate Physical Unclonable Functions (PUFs) that can distinguish between otherwise-identical fpga boards. This paper specifically introduces the first method for identifying cloud fpga instances by extracting a unique and stable fpga fingerprint based on PUFs measured from the fpga boards' DRAM modules. Experiments conducted on the Amazon Web Services (AWS) cloud reveal the probability of renting the same physical board more than once. Moreover, the experimental results show that hardware is not shared among f1.2xlarge, f1.4xlarge, and f1.16xlarge instance types. As the approach used does not violate any restrictions currently placed by Amazon, this paper also presents a set of defense mechanisms that can be added to existing countermeasures to mitigate users' attempts to fingerprint cloud fpga infrastructures.

关键词： Cloud fpgas Fingerprinting Physical Unclonable Functions PUFs DRAM PUFs Data Retention DRAM Refresh DRAM Decay

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Circuit partitioning with complex resource constraints in fpgas 98

Circuit partitioning with complex resource constraints in FP...

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Proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, fpga

作者： Liu, Huiqun Zhu, Kai Wong, D.F. Univ of Texas at Austin Austin TX United States

ISBN: (纸本)9780897919784

In this paper, we present an algorithm for circuit partitioning with complex resource constraints in large fpgas. Traditional partitioning methods estimate the capacity of an fpga device by counting the number of logic blocks, however this is not accurate with the increasing capacity and diverse resource types in the new fpga architectures. We propose a network flow based method to optimally check whether a circuit or a sub-circuit is feasible for a set of available heterogeneous resources. The feasibility checking procedure is integrated in the FM-based algorithm for circuit partitioning. Incremental flow technique is employed for efficient implementation. Experimental results on the MCNC benchmark circuits show that our partitioning algorithm not only yields good results, but also is efficient. Our algorithm for partitioning with complex resource constraints is applicable for both multiple fpga designs (e.g. logic emulation systems) and partitioning-based placement algorithms for a single large hierarchical fpga (e.g. Actel's ES6500 fpga family).

关键词： field programmable gate arrays

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