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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是321-330 订阅

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PyXEL: An Integrated Environment for the Analysis of Fault Effects in SRAM-Based fpga Routing 29

PyXEL: An Integrated Environment for the Analysis of Fault E...

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29th international symposium on Rapid System Prototyping, RSP 2018

作者： Bozzoli, Ludovica De Sio, Corrado Sterpone, Luca Bernardeschi, Cinzia Dipartimento di Automatica e Informatica Politecnico di Torino Torino Italy Department of Information Engineering University of Pisa Pisa Italy

ISBN: (纸本)9781538675571

In the last decades, fpgas have been increasingly used in many different mission critical applications, such as the avionics and aerospace ones. Thus, research interest in studying faults in fpgas has seen a sharp increase, especially for those applications that require high dependability and must operate in harsh environments. The increase of resources available in fpga devices has caused a huge growth in routing complexity. Nowadays, more than 80% of transistors in modern fpgas are related to the routing infrastructure. The analysis of faults related to routing structure of fpga devices is a hard task due to the lack of tools working at low-level, limited information availability about interconnection structure from vendors and, above all, no automated testing workflow for such kind of resources. In this paper, we introduce PyXEL, an integrated environment realized to automatize the analysis of fault effects in fpgas routing structure. PyXEL is a Python-based framework that allows to easily manipulate fpgas bitstreams in order to inject specific faults and to analyze their behavior. Moreover, PyXEL provides an easy way to build and run experimental workflow interacting directly with Xilinx Vivado and ISE allowing to select routing resources to test and logically analyze results. We demonstrated the feasibility and the advantages of our approach exploiting PyXEL to gain insight into the electrical effects of faults in the routing interconnections of the Xilinx Artix-7. © 2018 IEEE.

关键词： field programmable gate arrays (fpga)

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Accelerating 3D CNN-based Lung Nodule Segmentation on a Multi-fpga System 19

Accelerating 3D CNN-based Lung Nodule Segmentation on a Mult...

引用

Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Junzhong Shen Deguang Wang You Huang Mei Wen Chunyuan Zhang National University of Defense Technology changsha China National University of Defense Technology Changsha China National University of Defense Technology CHangsha China

ISBN: (纸本)9781450361378

Lung nodule segmentation is one of the most significant steps in many Computer Aided Detection (CAD) systems used for lung nodule identification and classification. Three-dimensional convolutional neural networks (3D CNNs) have become a promising method in lung nodule segmentation, as this method can achieve higher detection accuracy than conventional methods. It has been proven that fpgas can provide the most energy-efficient solution for CNN acceleration. However, the high computational complexity and memory requirements of 3D CNNs make it challenging to accelerate 3D CNNs on a single fpga, as this will further bottleneck the performance of a 3D CNN-based CAD system. Accordingly, in this work, we focus on accelerating the 3D CNN-based lung nodule segmentation on a multi-fpga platform by proposing an efficient mapping scheme that takes advantage of the massive parallelism provided by the platform, as well as maximizing the computational efficiency of the accelerators. Experimental results show that our system is able to achieve high computational efficiency and thereby a state-of-the-art performance of 14.5 TOPS at 200 MHz. Comparisons with CPU and GPU solutions demonstrate that our system achieves a 29.4x performance gain over CPU and a 10.5x energy efficiency improvement over GPU.

关键词： multi-fpga lung nodule segmentation 3d cnns

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How to Accelerate fpga Application in an Asynchronous Way? 19

How to Accelerate FPGA Application in an Asynchronous Way?

引用

Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Anping He Jilin Zhang Lvying Yu Pengfei Li Lian Li Lanzhou University Lanzhou China Lanzhou University Lanzhou China

ISBN: (纸本)9781450361378

fpga with massive customizable parallel computation capacity, is potentially good for fast time-to-market applications. However, its complex placing and routing lead to a relatively large latency and low frequency. Besides, the clock problems might make a design hard and slow, especially the one with complex control or variant computations. All of those defects seem to be from the essence of the synchronous design methodology and there does not exist an easy way to solve by clocks. Although the fpga vendors do not supply an asynchronous design routine, flow or tool, it is still possible to implement a clockless design with a concrete fpga chip and then harness lots of benefits that synchronous one misses, which is shown in this paper. We adopt link-joint as the asynchronous communication mechanism that discards clock limitation, but equips high throughput due to the fast handshake among neighbor clicks. The simplest link-joint circuit is click that conforms to Bundled Bound Data (BBD) protocol for local communication. Multiple clicks can be constructed and trimmed to types of micro-pipeline structures, feasibly and flexibly. With above considerations, we propose an innovative asynchronous design method for Xilinx fpga applications, as well as the asynchronous control framework by dedicated micro-pipeline structures. Furthermore, we introduce delay maching technologies as well as whole design flow and tool-chain. All of these supply an applicable way of accelerating an asynchronous design for a fpga. The case-studies show that communication between neighbor clicks is less than 1.1ns and the asynchronous method accelerates fpga latency extremely.

关键词： fpga click circuit asynchronous circuit

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fpga 2018 chairs’ welcome

FPGA 2018 - Proceedings of the 2018 ACM/SIGDA International ...

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fpga 2018 - Proceedings of the 2018 acm/sigda international symposium on field-programmable gate arrays 2018年 2018-February卷 iii页

作者： Bazargan, Kia Anderson, Jason H. University of Minnesota United States University of Toronto Canada

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XFER: A Novel Design to Achieve Super-Linear Performance on Multiple fpgas for Real-Time AI 19

XFER: A Novel Design to Achieve Super-Linear Performance on ...

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Weiwen Jiang Xinyi Zhang Edwin H.-M. Sha Qingfeng Zhuge Lei Yang Yiyu Shi Jingtong Hu University of Pittsburgh & Chongqing University Pittsburgh PA USA University of Pittsburgh Pittsburgh PA USA East China Normal University Shanghai China Chongqing University & University of California Irvine Irvine CA USA University of Notre Dame Notre Dame IN USA

ISBN: (纸本)9781450361378

Real-time inference with low latency requirement has become increasingly important for numerous applications in both cloud computing and edge computing. The fpga-based Deep Neural Network (DNN) accelerators have demonstrated the superior performance and energy efficiency over CPUs and GPUs; in addition, for real-time AI with low batch size, fpga is expected to achieve further performance improvement over the general purpose computing platform. However, the performance gain of the single-fpga design is hindered by the limited on-chip resource. In this paper, we leverage a cluster of fpgas to fully exploit the parallelism in DNNs with the objective of obtaining super-linear performance. To achieve this goal, a novel design, "XFER", is proposed to deploy DNNs to fpga cluster by splitting the DNN layer to multiple fpgas and moving traffics from memory bus to inter-fpga links. The resultant system can achieve both workload balance and traffic balance. As a case study, we implement Convolutional Neural Networks (CNNs) on ZCU102 fpga boards. Evaluation results demonstrate that XFER on two fpgas can achieve 3.48x speedup compared with state-of-the-art fpga designs, achieving super-linear speedup.

关键词： real-time inference super-linear performance multi-fpga cluster

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Storage Mirroring for Bare-Metal Systems on fpga Devices 19

Storage Mirroring for Bare-Metal Systems on FPGA Devices

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Dan Cristian Turicu Octavian Cret Lucia Vǎcariu Bitdefender Technical University of Cluj-Napoca Cluj-Napoca Romania Technical University of Cluj-Napoca Cluj-Napoca Romania

ISBN: (纸本)9781450361378

Malicious applications, malware, continue to be a major security threat for computer systems. Due to the fast growing number and increasing complexity of malware, manual analysis became impractical and automated methods are preferred by security analysts. The automated dynamic analysis of malware executes the samples in controlled environments and monitors the execution for potentially malicious behavior. The vulnerability of this method is that modern malware detect these emulated or virtualized environments and suspend their malicious activities to foil the analysis. However, the malware exhibit a semantically different behavior when running directly on computer system hardware, i.e. bare-metal systems. Consequently, the ultimate technique for analyzing the behavior of malware is through execution of the samples in bare-metal analysis environments. Nevertheless, restoring the system to a clean state after each sample analysis is challenging. In order to restore the storage device state of a bare-metal system to a clean state, in this paper we propose an fpga-implemented storage mirroring technique for instantaneous restoration of the storage device and, optionally, the retrieval of the files having been modified during the sample execution. The fpga-based system can be integrated in commodity computer systems with Serial ATA storage devices. The retrieval of modified files is supported for systems running Windows operating systems with NTFS file-system. The experimental results demonstrate the viability of the solution.

关键词： storage restore storage mirroring serial ata devices fpga bare-metal malware analysis

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A Hybrid Data-Consistent Framework for Link-Aware AccessManagement in Emerging CPU-fpga Platforms 19

A Hybrid Data-Consistent Framework for Link-Aware AccessMana...

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Liang Feng Jieru Zhao Tingyuan Liang Sharad Sinha Wei Zhang Hong Kong University of Science and Technology Hong Kong Hong Kong Indian Institute of Technology Goa Goa India

ISBN: (纸本)9781450361378

To satisfy the increasing demands of modern computing tasks, heterogeneous computing is gaining attention. The CPU-fpga platform is especially promising since the fpga enables customization for diverse computing tasks to be offloaded from the CPU to boost the performance and energy efficiency. Nowadays, tightly coupled CPU-fpga platforms with shared coherent caches (such as the Intel HARP and IBM POWER with CAPI) have been proposed for enhanced CPU-fpga data communication efficiency and a simplified programming model. In Intel's recently released CPU-fpga platform HARP2, there are three links between the XEON multi-core CPU and the Arria 10 fpga, two PCIes and one QPI, with a coherent fpga cache attached before the QPI for the quick memory access and data locality benefit. The link choice for the fpga memory accesses will heavily influence the performance in such platforms and the race among links may violate the data consistency. In order to enhance the performance and maintain the data consistency, we propose COODA, a static and dynamic hybrid framework for memory access management in HARP2-like emerging CPU-fpga platforms. COODA adaptively arranges the memory accesses to the preferred link to boost the fpga cache benefit and enhance the utilization of all links. An automatic data consistency maintenance mechanism based on the static analysis is also applied by COODA to keep the whole data consistency. Based on implementation results on the real Intel HARP2 platform for diverse applications, COODA is shown to improve the performance a lot compared with the state-of-the-art methods.

关键词： cache memory heterogeneous computing fpga data consistency

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Engaging Heterogeneous fpgas in the Cloud 19

Engaging Heterogeneous FPGAs in the Cloud

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Ke Zhang Yisong Chang Mingyu Chen Yungang Bao Zhiwei Xu ICT CAS University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781450361378

fpga has become an essential infrastructural component in commercial cloud and datacenter for improving system performance and efficiency. Meanwhile, a heterogeneous fpga chip (Hetero-fpga) in which a multi-core System-on-Chip (SoC) is tightly integrated with an fpga fabric has been successfully pioneered. Given its hardware-software co-programmability, Hetero-fpga is supposed to become an independent and first-class cloud computing resource with networking capabilities in order to avoid involving brawny commodity x86 servers as carriers for fpga fabrics which are usually the cases in current commercial fpga clouds from several web vendors. Following this design paradigm, we present HeFA, a self-contained Hetero-fpga Array architecture in cloud. We construct a high-level hardware template as well as a software stack for the Hetero-fpga node, enabling the SoC as a primary engine to manage, coordinate and incorporate with the dominant fpga fabric. We also propose a fully scripted design flow to make HeFA as an easy-to-use cloud infrastructure. Based on these techniques, we implement an academia prototype chassis of HeFA that includes 32 Hetero-fpga nodes with Xilinx's Zynq MPSoC chips. By a customized cloud resource manager, the prototype is flexibly provisioned as either 32 individual fpga nodes or multiple scalable sub-clusters to abstract arbitrary volume of reconfigurable fabrics as on-demand cloud services. In this manner, a versatile research and educational platform is delivered for agile hardware-software co-design in scenarios such as domain-specific accelerator development, open instruction set architecture-based chip design, computer system-related experimental project, and so on.

关键词： hardware template fpga array cloud computing software stack scripted design flow

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Unleashing the Power of Soft Logic for Convolutional Neural Network Acceleration via Product Quantization 19

Unleashing the Power of Soft Logic for Convolutional Neural ...

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Jialiang Zhang Jing Li University of Wisconsin-Madison Madison WI USA

ISBN: (纸本)9781450361378

To reduce the load of taxing CNN infrastructures, both industry and academia show great interest in building specialized hardware for CNN acceleration. Numerous fpga-based accelerators have been proposed to better utilize hard blocks. However, the capability of soft logic has not been fully explored. Prior works either fail to utilize soft logic for computation or inefficiently use soft logic to mimic the function of hard blocks. In this work, to better utilize soft logic we propose to use the native function of soft logic, i.e. as distributed memory, which yields more than 20x throughput compared to implementing multiplication operations. To fully leverage this potential, we present a framework to more efficiently accelerate CNN-based inference. Firstly, we employ product quantization (PQ) to convert most of the multiplications to a reduced number of distributed memory accesses and additions. We then constructed an analytical model to reveal the complex relationship between the inference accuracy and the utilization of hard blocks and soft blocks. Based on the model, we select optimal PQ parameters for a balanced design. In the rest of this paper, we describe the complete system implementation and discuss the experimental results. According to our results on Xilinx VU9P fpga, we can achieve a 140 Tops equivalent throughput and 475 Gops/W energy efficiency with less than 0.5% accuracy degradation.

关键词： cnn product quantization fpga

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Building fpga State Machines from Sequential Code 19

Building FPGA State Machines from Sequential Code

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Carl-Johannes Johnsen Kenneth Skovhede University of Copenhagen Copenhagen Denmark

ISBN: (纸本)9781450361378

State machines are commonly used and well understood for hardware. However, in some cases they can introduce complexity as the program can no longer be read sequentially. We propose an extension to the SME model, which retains the sequential program structure, by using a barrier-like 'await' construct to divide a program into states. This is done by awaiting a predicate, ensuring that the sequential program does not progress until the predicate is satisfied. This initial implementation enables the clock signal as a predicate, allowing for easy partitioning of the sequential program, which is a common approach when either pipelining or sequencing a problem. Future implementations will also enable functions or signal values as predicates. The signal values will be a simple to use barrier when waiting for external input. As for the functions, it handles all the communication regarding input/output for and synchronization with the function. As always with the SME model, the problems implemented in the model can be transpiled into VHDL along with a VHDL test bench, which verifies that the generated VHDL matches the SME simulation. Our preliminary results shows that Xilinx Vivado recognises the state machines and that the SME simulation is clock cycle accurate to the simulation of the generated VHDL. Furthermore, we see reduced resource consumption and higher clock rates, as we should by leveraging state machines, without increasing the complexity and readability of the original program.

关键词： vhdl sme fpga code complexity async state machine await hls

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