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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

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Scalable High Performance SDN Switch Architecture on fpga for Core Networks 19

Scalable High Performance SDN Switch Architecture on FPGA fo...

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Sasindu Wijeratne Ashen Ekanayake Sandaruwan Jayaweera Danuka Ravishan Ajith Pasqual University of Moratuwa Moratuwa Sri Lanka

ISBN: (纸本)9781450361378

Due to the increasing heterogeneity in network user requirements, dynamically varying day to day network traffic patterns and delay in network service deployment, there is a huge demand for scalability and flexibility in modern networking infrastructure, which in return has paved way for the introduction of Software Defined Networking (SDN) in core networks. In this paper, we present an fpga-based switch which is fully compliant with OpenFlow; the pioneering protocol for southbound interface of SDN. The switch architecture is completely implemented on hardware. The design consists of an OpenFlow Southbound agent which can process OpenFlow packets at a rate of 10Gbps. The architecture contains a primary pipeline which is capable of achieving core network throughputs and an auxiliary pipeline leading to the Openflow agent. Single clock cycle Content Accessible Memory (CAM) architecture supports the overall design to achieve its throughput and latency requirements. The proposed architecture speed scales up to 400Gbps while it consumes only 60% resources on a Xilinx Virtex-7 featuring XC7VX485T fpga. Switch fabric is capable of connecting to a control plane running upon a host PC via PCIe which provides an opportunity at research level to explore SDN in core networks. Moreover, the architecture is experimented for different scaled versions using line rates of 10G, 25G and 100G. By using fpga based embedded platforms which support sufficient number of ports and their line rates, this architecture can be deployed in core networks.

关键词： pcie core network fpga openflow software defined networking content accessible memory

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PVT-Aware Sensing and Voltage Scaling for Energy Efficient fpgas 19

PVT-Aware Sensing and Voltage Scaling for Energy Efficient F...

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Konstantinos Maragos George Lentaris Dimitrios Soudris Vasilis F. Pavlidis National Technical University of Athens Athens Greece The University of Manchester Manchester United Kingdom

ISBN: (纸本)9781450361378

In this work we introduce a method to improve the energy efficiency of the fpga devices by reducing the pessimistic operation guardbands posed by the commercial EDA tools. The proposed method bases on a voltage scaling scheme that reliably decreases the supply voltage. We deploy a uniform network of delay-based sensors across the fabric of the fpga to sense all process, voltage and temperature variation (PVT) effects. The delay of all the sensors is calibrated to match the worst critical path delay of the target application. In that respect, the monitoring of the sensor network enables the indirect assessment of the functional integrity of the target application. The distributed placement of the sensors provides the desired sensitivity with appropriate granularity across the fabric and allows us to consider the worst-case scenario. The sensor network is integrated during the development cycle as ready-to-use software IP with negligible resource overhead, for example, 1-2% of a Zynq XC7Z020 fpga for 10 sensors. The sensitivity of the sensors to all PVT variations and the correlation with the application operation is verified through extensive testing by using multiple fpgas and realistic benchmarks. The aforementioned approach facilitates a closed-loop voltage scaling scheme to regulate the supply voltage and reduce the power of the system. In our experiments on a set of 28nm Xilinx XC7Z020 SoC fpgas and realistic digital signal processing (DSP) benchmarks, we demonstrate up to 27.2% decrease in power for 13% decrease in voltage, while retaining the nominal timing performance.

关键词： voltage scaling process variation fpga voltage variation temperature variation

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Design and Implementation of a Deterministic fpga Router on a CPU+fpga Acceleration Platform 19

Design and Implementation of a Deterministic FPGA Router on ...

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Dario Korolija Mirjana Stojilovic École Polytechnique Fédérale de Lausanne Lausanne Switzerland

ISBN: (纸本)9781450361378

fpga routing is one the longest steps in fpga compilation, often preventing fast edit-compile-test cycles in prototyping and development. There have been attempts to accelerate fpga routing using algorithmic improvements, multi-core or multi-CPU platforms. Instead, we propose porting fpga routing to a CPU+fpga platform. Motivated by the approaches in fpga-accelerated graph processing, we propose and implement three acceleration strategies: (1) reducing the number of expensive random memory accesses, (2) parallel and pipelined computation, and (3) efficient hardware priority queues. To reduce irregular memory accesses we first allow wire-to-pin wavefront expansion only when a net is reaching one of its destination pins and, second, we group in sets all the wires starting at the same (x, y) coordinate of the fpga grid and going in the same direction. Consequently, it becomes possible to design an fpga accelerator that performs streaming memory accesses and parallel wavefront expansion on all wires in two connected sets. To test and evaluate our fpga-accelerated PathFinder-based router, we implement it on DE1-SoC, Intel's ARM+fpga platform and run a set of benchmarks from the VTR suite. The results show that our implementation produces deterministic and good quality output. It is also successful in accelerating a purely software version on the same CPU+fpga platform, but not against VPR running on a powerful Intel Core-i5 CPU, due to the limitations of the chosen mid-end DE1-SoC platform. Yet, our performance prediction model suggests that higher memory bandwidth and faster FP units would render our router superior to the software alternative.

关键词： pathfinder arm fpga routing hw/sw co-design hardware acceleration parallel maze expansion

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A Deep-Reinforcement-Learning-Based Scheduler for High-Level Synthesis 19

A Deep-Reinforcement-Learning-Based Scheduler for High-Level...

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Hongzheng Chen Minghua Shen Sun Yat-sen University Guangzhou China

ISBN: (纸本)9781450361378

As the most important stage in high-level synthesis (HLS), scheduling mostly relies on heuristic algorithms due to their speed, flexibility, and scalability. However, designing heuristics easily involves human bias, which makes the scheduling unpredictable in some specific cases. In this paper, we propose a deep-reinforcement-learning (Deep-RL) based scheduler for HLS. It maximumly reduces the human involvement and learns to schedule by itself. Firstly, we introduce a novel state and action representation for constrained scheduling problems, which is the foundation of the learning task. Secondly, we use a training pipeline to train the policy network. Supervised learning is used to initialize the weight of the network, and reinforcement learning is used to improve the performance, which makes the Deep-RL based scheduler practical for HLS. Finally, we compare our scheduler with the ASAP schedule and the optimal ILP schedule. Experimental results show our scheduler can reduce up to 74% resource usage compared with the original ASAP schedule, and the gap between the optimal solution is small. Notably, this is the first work leveraging reinforcement learning in HLS and has great potential to be integrated into different HLS systems.

关键词： fpga scheduling deep reinforcement learning high-level synthesis

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Transistor-Level Optimization Methodology for GRM fpga Interconnect Circuits 19

Transistor-Level Optimization Methodology for GRM FPGA Inter...

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Zhengjie Li Yuanlong Xiao Yufan Zhang Yunbing Pang Jian Wang Jinmei Lai Fudan University Shanghai China

ISBN: (纸本)9781450361378

Due to its dominance in the whole chip area, power and delay, the fpga interconnect circuits are traditionally designed by full custom design method. We present an automated transistor-level sizing optimization methodology for GRM fpga interconnect circuits. In order to get accurate and effective predicated area, the commonly used diffusion sharing, transistor folding and inputs sharing are considered. To get the accurate and effective delay value, we avoid the inaccuracy of using linear device model, and use two schemes to build wire model: the wire within a circuit and the wire between interconnect circuits. To decrease simulation time, we propose multi-thread acceleration method and the Minimum-Final-Delay (MFD) algorithm which optimizes interconnect circuit as a whole, not separated part. For switch box optimization, MFD algorithm requires 38% less number of simulations than COFFE's algorithm. We use 65nm CMOS process technology for evaluation. For different optimization strategy, we emphasize either representative critical path delay or overall layout area. Compare to full-custom design method, the global cost can be decrease by 3% ~ 17%. For different transistor sizing combinations, 10/50 threads can be ~ 9X/15X faster than single-thread. Compared with the manual design method, our optimization methodology explores larger design space, and it decreases the circuit design optimization time from months to hours.

关键词： transistor-level optimization wire load model multi-thread acceleration minimum-final-delay algorithm area model

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PAI-FCNN: fpga Based CNN Inference System 19

PAI-FCNN: FPGA Based CNN Inference System

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Lansong Diao Zhao Jiang Hao Liang Chang'an Ye Kai Chen Li Ding Shunli Dou Meng Sun Lixue Xia Jiansong Zhang Wei Lin Alibaba Group Beijing China Alibaba Group Hangzhou China

ISBN: (纸本)9781450361378

We describe the fpga subsystem of the Platform of Artificial Intelligence (PAI) in Alibaba Group, called PAI-FCNN. PAI-FCNN plays the role of a heterogeneous back-end for CNN inference, together with other CPU, GPU and ASIC subsystems in PAI. Driven by various business needs, we built PAI-FCNN from scratch since two years ago. We present our experience from fpga/compiler design and implementation, to system evaluation and deployment. In particular, in order to address three practical challenges: (1) Efficient processing for diverse operators and model structure such as Deconv, Dilated Conv, Up-sampling, PReLu and Concatenation. (2) Serving multiple highly-different models on single fpga hardware. (3) Competitive performance with alternative GPU or ASIC solutions, we extensively perform joint software & hardware design to optimize system efficiency across multiple CNN models, which includes model reconstruction in compiler software and flexible data access in data-flow CNN processor. We also incorporate reduced precision and model retraining to boost system capacity. Using U-net as an example, on Xilinx KU115 chip, with the help of 74.9% efficiency on Int16-precision hardware (with 3.226TOPS capacity) and 72.9% efficiency on mixed-int8/int3-precision hardware (with 14.746TOPS capacity), we achieve slightly better throughput and 2X higher power efficiency than P4.

关键词： reduced precision inference compiler system joint software & hardware design cnn

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A fully onchip binarized convolutional neural network fpga impelmentation with accurate inference 18

A fully onchip binarized convolutional neural network FPGA i...

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23rd IEEE/acm international symposium on Low Power Electronics and Design, ISLPED 2018

作者： Yang, Li He, Zhezhi Fan, Deliang Department of Electrical and Computer Engineering OrlandoFL United States

ISBN: (纸本)9781450357043

Deep convolutional neural network has taken an important role in machine learning algorithm which has been widely used in computer vision tasks. However, its enormous model size and massive computation cost have became the main obstacle for deployment of such powerful algorithm in low power and resource limited embedded system, such as fpga. Recent works have shown the binarized neural networks (BNN), utilizing binarized (i.e. +1 and -1) convolution kernel and binary activation function, can significantly reduce the model size and computation complexity, which paves a new road for energy-efficient fpga implementation. In this work, we first propose a new BNN algorithm, called Parallel-Convolution BNN (i.e. PC-BNN), which replaces the original binary convolution layer in conventional BNN with two parallel binary convolution layers. PC-BNN achieves ∼86% on CIFAR-10 dataset with only 2.3Mb parameter size. We then deploy our proposed PC-BNN into the Xilinx PYNQ Z1 fpga board with only 4.9Mb on-chip RAM. Since the ultra-small network parameter, it is feasible to store the whole network parameter into on-chip RAM, which could greatly reduce the energy and delay overhead to load network parameter from off-chip memory. Meanwhile, a new data streaming pipeline architecture is proposed in PC-BNN fpga implementation to further improve throughput. The experiment results show that our PCBNN based fpga implementation achieves 930 frames per second, 387.5 FPS/Watt and 396×10-4 FPS/LUT, which are among the best throughput and energy efficiency compared to most recent works. © 2018 Association for Computing Machinery.

关键词： field programmable gate arrays (fpga)

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A fpga Implementation of Farneback Optical Flow by High-Level Synthesis 19

A FPGA Implementation of Farneback Optical Flow by High-Leve...

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Chia-Wei Chang Zi-Qi Zhong Jing-Jia Liou National Tsing Hua University HsinChu Taiwan Roc

ISBN: (纸本)9781450361378

Optical flow algorithm, which estimates the motion detection of consequent video frames, is widely used in surveillance system, Advanced Driver Assistance Systems (ADAS) and object movement estimation in scene analysis. Among different optical flow algorithms, Farneback version provides a better accuracy and brightness-change-resistant displacements by estimating the flow from polynomial domain rather than intensive maps. However, high computation complexity and inconsistent data access patterns make it difficult to be implemented on a hardware platform. In this work, we present a micro-architecture design of Farneback optical flow, which is flexible for optimization with high level Synthesis (HLS) tools. The original software-based implementation was decomposed into functional blocks to balance latency of different stages and flows of data were rearranged to accommodate better memory access patterns. The data flow arrangement is based on a proposed backtrace mechanism, where DRAM accesses of polynomial coefficients in current frame makes consistent traffic patterns, and therefore make it possible to integrate more functional blocks into a deeper pipeline. For several micro-architecture design versions, we demonstrate options of fixed and floating points, optimization techniques such as multiple DMAs and different levels of pipeline integration. We implemented our design on Zedboard Mini-ITX 7045. The results show a 17x end-to-end speedup against a naive HLS version with an image size of 160x120. Considering only the hardware-accelerated part, our fpga implementation is 40x faster than the naive HLS version with only 50% of the fpga hardware resources.

关键词： hardware accelerators optical flow high-level synthesis fpga

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Flat fpga Fabrics Derived from 2D-Benes-BFT-Pyramid Networks with Optimizations and Enhancements 19

Flat FPGA Fabrics Derived from 2D-Benes-BFT-Pyramid Networks...

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Venkat Konda Konda Technologies Inc. San Jose CA USA

ISBN: (纸本)9781450361378

Hierarchical fpga fabrics based on 2D-BFT-Pyramid networks with transformations and optimizations even though offer significant area, power and performance savings still have several drawbacks compared to 2D-Mesh based fpga fabrics. For example, hierarchical multi-stage fabrics are replicated at tile level of certain tile size do not offer consistent results regardless of the placement of the benchmarks emulated and certain precious routing resources are usable only if the signal traverses that particular hierarchy. We present several enhancements, techniques, and optimizations to transform hierarchical multi-stage networks into flat multi-stage networks i.e., make them replicable for each logic block in both multiplexers and wires. We also propose techniques to provide cascadable wires of arbitrary length with single multiplexer delay to traverse several wires of signal path or same stage connections, to enable multiple signal U-turns as opposed to only one U-turn inherent in a multi-stage network. We achieved the goal of making multi-stage network based fpga fabric to seamlessly replace any existing 2D-Mesh based fabric, yet keeping everything else intact including placement, routing and all CAD Tools. We implemented the flat multi-stage networks based fpga fabrics in a few commercial fpgas with ~3X area savings and significant improvements in other dimensions and also the routing runtime in parity. We conclude with illustration of the benefits and absolutely no drawbacks for multi-stage network based Flat fpga fabrics compared to prevailing 2D-Mesh network based fabrics. The foregoing Flat fpga Fabric technology was patent protected since September 7, 2011 in US9374322, US9509634 and their continuation patents.

关键词： flat fpga fabrics fpga fabrics 2d-bft-pyramid networks 2d-bft networks 2d-multi-stage networks hierarchical fpga fabrics 2d-benes networks multi-stage fpga fabrics

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Speedy: An Accelerator for Sparse Convolutional Neural Networks on fpgas 19

Speedy: An Accelerator for Sparse Convolutional Neural Netwo...

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Liqiang Lu Yun Liang Ruirui Huang Wei Lin Xiaoyuan Cui Jiansong Zhang Peking University Beijing China Alibaba Group Beijing China

ISBN: (纸本)9781450361378

Deep convolutional neural networks (CNNs) have achieved remarkable performance with the cost of huge computation. Moreover, the current trend of CNNs is towards more complex and deeper topology. Compressing CNNs to sparse have emerged as the most attractive approach to reduce the amount of computation and memory requirement. This compression is achieved by pruning the redundant connection in networks. fpgas have been an effective solution to accelerate CNN inference for its high parallel computing, flexibility and energy-efficiency. Although existing fpga architectures are able to excellently process dense CNN models, they cannot benefit from the computation reduction when accelerating the sparse CNN models. Because most of the arithmetic operations involve addition and multiplication with zero operands, meanwhile accelerating sparse CNN models incurs significant data encoding and decoding overhead. In this paper, we propose a fpga accelerator Speedy that can efficiently exploit sparsity in CNN models. We first investigate the dataflow design space to explore the available performance with different parallelization strategies. The result of exploration is Speedy dataflow which provides enough parallel multiplications and maximizes the weight reuse. Then, we propose a novel data representation combined with memory partition technique to increase the on-chip bandwidth. Finally, we propose Speedy fpga architecture in which we apply line buffer design and high-throughput PE. In the experiments, we evaluate Speedy on contemporary neural networks. Speedy provides flexible parameters for different fpga scale. First, we evaluate the resources utilization and hardware efficiency with different design configurations. Then we compare our design with previous fpga implementations. Overall, Speedy achieves 11.3x-20.8x and 1.5x-6.8x speed up for Alexnet and VGGnet with 90% weight sparsity.

关键词： sparse fpga cnn

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