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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

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A Reconfigurable Accelerator for Sparse Convolutional Neural Networks 19

A Reconfigurable Accelerator for Sparse Convolutional Neural...

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Weijie You Chang Wu Fudan University Shanghai China

ISBN: (纸本)9781450361378

Convolutional Neural Networks (CNNs) have been shown to be very useful in image recognition and other AI applications. CNNs are usually computationally intensive. To address the challenge of overwhelming calculation requirements, researchers have proposed network compression methods to reduce the number of synaptic weights and the amount of computations. In this paper, we propose an input row based sparse convolution neural network accelerator on fpgas that performs sparse CNN computing efficiently. Similar to the DNNWEAVER architecture, our accelerator also uses two-level architecture hierarchy, with multiple Processing Units (PUs) and each PU comprises a set of basic Processing Elements (PEs). The number of PEs in a single PU and the number of PUs in a design are reconfigurable for different CNNs for best performance. Our architecture does not require the large multiplexer for data selection as needed in Cambricon-X, thus, is more suitable for larger accelerator designs for high performance. Besides, we propose a weight merging method to balance the computation load on different PUs to maximize the overall computation efficiency. For evaluation, we implement our design with 32 PUs and each with 14 PEs. When compared with the DNNWEAVER implementation for non-sparse VGG16 network, we get an overall performance of 3.6x speedup running at 100MHz on a Xilinx ZC706 board and reach the speed of 297 GOPS.

关键词： accelerator sparse convolution neural networks fpga

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Optimizing Order-Associative Kernel Computation with Joint Memory Banking and Data Reuse 19

Optimizing Order-Associative Kernel Computation with Joint M...

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Juan Escobedo Mingjie Lin University of Central Florida Orlando FL USA

ISBN: (纸本)9781450361378

In this paper, we develop a joint strategy of memory banking and data reuse to specifically optimize the memory performance of any given order-associative and stencil-based computing kernel i.e., its iteration order can be reordered freely without compromising its correctness. Given any shape of stencil kernel, our methodology can achieve throughput of 1 kernel per clock cycle with only two memory banks and two data reuse buffers of constant small buffer sizes provided order-associativeness is given. This is a huge leap over all existing results for general stencil-based computing, where, depending the specific data reuse method, either a number of data reuse buffers proportional to the stencil size are required or a potentially problem-dependent reuse buffer size is needed. Furthermore, the optimal memory partition factor of existing methods is typically proportional to the actual stencil size of a given kernel, whereas in our method, the number of memory banks remains to be 2 irrespective of the stencil shape and size. On average, when compared with the mainstream methods, our approach achieves approximately 30-70% reduction in hardware usage, while improving performance by about 15%. Moreover, the number of independent memory banks required to accomplish conflict-free data accesses have dropped by more than 30%.

关键词： data reuse fpga hls memory partition

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OLAF′17: Third international Workshop on Overlay Architectures for fpgas 17

OLAF′17: Third International Workshop on Overlay Architectu...

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acm/sigda international symposium on field-programmable gate arrays

作者： So, Hayden Kwok-Hay Wawrzynek, John Univ Hong Kong Dept Elect & Elect Engn Hong Kong Peoples R China Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA

ISBN: (纸本)9781450343541

The Third international Workshop on Overlay Architectures for fpgas (OLAF) is held in Monterey, California, USA, on Feburary 22, 2017 and co-located with fpga 2017: The 25th acm/sigda international symposium on field programmable gate arrays. The main objective of the workshop is to address how overlay architectures can help address the challenges and opportunites provided by fpga-based reconfigurable computing. The workshop provides a venue for researchers to present and discuss the latest developments in fpga overlay architecture and related areas. We have assembled a program of six refereed papers with panel discussions with prominent experts in the field.

关键词： fpga Overlay architecture

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Towards Fast and Energy-Efficient Binarized Neural Network Inference on fpga 19

Towards Fast and Energy-Efficient Binarized Neural Network I...

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Cheng Fu Shilin Zhu Hao Su Ching-En Lee Jishen Zhao Iluvatar CoreX & University of California San Diego La Jolla CA USA University of California San Diego La Jolla CA USA Iluvatar CoreX San Jose CA USA

ISBN: (纸本)9781450361378

Binarized Neural Network (BNN) removes bitwidth redundancy in classical CNN by using a single bit (-1/+1) for network parameters and intermediate representations, which has greatly reduced the off-chip data transfer and storage overhead. However, a large amount of computation redundancy still exists in BNN inference. By analyzing local properties of images and the learned BNN kernel weights, we observe an average of ~78% input similarity and ~59% weight similarity among weight kernels, measured by our proposed metric in common network architectures. Thus there does exist redundancy that can be exploited to further reduce the amount of on-chip *** by the observation, in this paper, we proposed two types of fast and energy-efficient architectures for BNN inference. We also provide analysis and insights to pick the better strategy of these two for different datasets and network models. By reusing the results from previous computation, much cycles for data buffer access and computations can be skipped. By experiments, we demonstrate that 80% of the computation and 40% of the buffer access can be skipped by exploiting BNN similarity. Thus, our design can achieve 17% reduction in total power consumption, 54% reduction in on-chip power consumption and 2.4× maximum speedup, compared to the baseline without applying our reuse technique. Our design also shows 1.9× more area-efficiency compared to state-of-the-art BNN inference design. We believe our deployment of BNN on fpga leads to a promising future of running deep learning models on mobile devices.

关键词： energy efficiency input reuse fpga weight reuse acceleration binarized neural networks

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A Pixel-Parallel Virtual-Image Architecture for High Performance and Power Efficient Graph Cuts Inference 19

A Pixel-Parallel Virtual-Image Architecture for High Perform...

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Tianqi Gao Rob A. Rutenbar University of Illinois at Urbana Champaign Urbana Champaign IL USA University of Pittsburgh Pittsburgh PA USA

ISBN: (纸本)9781450361378

A Pixel-Parallel Virtual-Image Architecture for High Performance and Power Efficient Graph Cuts Inference Tianqi Gao, University of Illinois Urbana Champaign Rob A. Rutenbar, University of Pittsburgh Contact: [email protected] Graph Cuts is a popular technique for Maximum A Posteriori inference in computer vision. It transforms a Markov Random field problem into a network flow problem, solved via the Push-Relabel algorithm. While attractively simple, the large size of a typical image and the large number of necessary pixel-level iterations render the technique computationally expensive. Prior accelerator attempts have been reported with GPUs and fpgas. In [1], the first pixel-parallel architecture was demonstrated in fpga, but limited to only 256-pixel images. This paper extends this pixel-parallel concept and makes following contributions: a "Virtual Image" architecture solves the size limitation: large images are decomposed into "tiles", and "stacked" on the physical processor array; appropriate addressing mechanisms handle virtual pixels and a range of tile edge effects; scaling up the processor array to 1536 pixels; a novel and hardware-friendly heuristic shortens the convergence. We demonstrate the first working virtual-image Graph Cuts accelerator, applied to standard 640x480 images. Scaling up the hardware and the new heuristic bring 6.5x and 1.65x speedups respectively compared with [1]. The design is 7-20x faster than prior fpga designs, and roughly comparable in speed to a modern GPU benchmark. However, the architecture also offers significant performance-per-unit-power advantages. Formulating a figure of merit particularly for Graph Cuts inference - Graph Cuts per second per Watt - our architecture is about 4 times better than other implementations. Keywords: fpga; Machine learning; Hardware Acceleration; Computer Vision DOI: https://***/10.1145/3289602.3293948

关键词： machine learning hardware acceleration fpga computer vision

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Maverick: A Stand-alone CAD Flow for Xilinx 7-Series fpgas 19

Maverick: A Stand-alone CAD Flow for Xilinx 7-Series FPGAs

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Dallon Glick Jesse Grigg Brent Nelson Michael Wirthlin NSF Center for Space High-Performance and Resilient Computing (SHREC) & Brigham Young University Provo UT USA

ISBN: (纸本)9781450361378

Traditionally, an fpga vendor's own set of computer-aided design (CAD) tools are used to generate circuits for a given vendor's fpgas. However, numerous non-vendor CAD tools have been introduced to supplement the vendor-provided tools, allowing novel ideas to be explored and a variety of technical challenges to be addressed. This poster presents Maverick, a stand-alone CAD flow for compiling Verilog to bitstreams for Xilinx 7-Series devices. After an initial configuration design is created with Xilinx's Vivado partial reconfiguration (PR) flow to define a static design and a PR region, the Maverick flow can then compile and map Verilog design into that PR region - without the use of vendor tools. The Maverick flow combines two existing open source projects (Yosys and Project X-Ray) with our own RapidSmith2 tools to form an end-to-end compilation flow. It uses Yosys (synthesis), RapidSmith2 (pack, place, route), and the Project X-Ray tools (bitstream generation), taking Verilog designs as input and generating partial bitstreams as output. Several modifications were made to these existing tools and completely new tools were created, including a new RapidSmith2-based router, as a part of this work. This poster details these CAD steps and shows the results of the CAD flow running on a PYNQ-Z1 SoC's ARM processor to compile a set of HDL designs to partial bitstreams. The resulting bitstreams were configured onto the PYNQ-Z1's fpga fabric, demonstrating the feasibility of a single-chip system which can both compile HDL designs to bitstreams and then configure them onto its own fabric.

关键词： reconfigurable computing 3rd party fpga cad flows methods place & route algorithm design techniques

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Hierarchical fpga Fabrics using 2D-Benes-BFT-Pyramid Network Layouts with Optimizations 19

Hierarchical FPGA Fabrics using 2D-Benes-BFT-Pyramid Network...

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Venkat Konda Konda Technologies Inc. San Jose CA USA

ISBN: (纸本)9781450361378

Even though Benes/BFT multi-stage networks offer O(N*Log N) crosspoint complexity compared to 2D-Mesh Networks with O(N^2) crosspoint complexity, lack of known 2D-Mesh-like 2D layouts for multi-stage networks is the first main hurdle to exploit them as an fpga fabric and consequently 2D-Mesh based fabrics have become prevalent. First, we present a fundamental layout for Benes/BFT networks making them implementable as simple as 2D-Mesh Networks, with all the wires between different logic blocks as either horizontal wires or vertical wires only, so we named them 2D-Benes or 2D-BFT Networks or 2D-Multi-stage networks in general. We apply several isomorphic transformations, and adapt Pyramid network properties. We also provide locality or nearest neighborhood connectivity, so that each logic block is directly connected its four neighbors and each logic block is connected to all its neighbors with the same path length or delay by bringing nearest neighbor connections to lower stages. Since fully connected Benes/BFT Networks is an over-kill as an fpga fabric, we adapt several ways of crossbar depopulation and wire segmentation. We implemented various hierarchical multi-stage networks based fpga fabric architectures, replicable at tile level, in a commercial fpga and achieved ~2X area savings with significant power and performance improvements over 2D-Mesh based fabrics. We conclude with a summary of the benefits and drawbacks of these multi-stage networks based Hierarchical fpga fabrics compared to prevailing 2D-Mesh network based fabrics. The foregoing Hierarchical fpga Fabric technology was patent protected since May 25, 2007 in US8269523, US8898611, US9374322, US9509634 and their continuation patents.

关键词： multi-stage fpga fabrics hierarchical fpga fabrics 2d-bft-pyramid networks fpga fabrics flat fpga fabrics 2d-bft networks 2d-multi-stage networks 2d-benes networks

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Fast Confidence Detection: One Hot Way to Detect Adversarial Attacks via Sensor Pattern Noise Fingerprinting 19

Fast Confidence Detection: One Hot Way to Detect Adversarial...

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Yazhu Lan Qingli Guo Guohe Zhang Yuanchao Xu Kent W. Nixon Hai Helen Li Yiran Chen Duke University Durham NC USA University of Chinese Academy of Sciences Beijing China Xi'an Jiaotong University Xi'an China Capital Normal University Beijing China

ISBN: (纸本)9781450361378

Deep Neural Networks (DNNs) have shown phenomenal success in a wide range of real-world applications. However, a concerning weakness of DNNs is that they are vulnerable to adversarial attacks. Although there exist methods to detect adversarial attacks, they often suffer constraints on specific attack types and provide limited information to downstream systems. We specifically note that existing adversarial detectors are often binary classifiers, which differentiate clean or adversarial examples. However, detection of adversarial examples is much more complicated than such a scenario. Our key insight is that the confidence probability of detecting an input sample as an adversarial example will be more useful for the system to properly take action to resist potential attacks. In this work, we propose an innovative method for fast confidence detection of adversarial attacks based on integrity of sensor pattern noise embedded in input examples. Experimental results show that our proposed method is capable of providing a confidence distribution model of most of popular adversarial attacks. Furthermore, our presented method can provide early attack warning with even the attack types based on different properties of the confidence distribution models. Since fast confidence detection is a computationally heavy task, we propose an fpga-Based hardware architecture based on a series of optimization techniques, such as incremental multi-level quantization and etc. We realize our proposed method on an fpga platform and achieve a high efficiency of 29.740 IPS/W with a power consumption of only 0.7626W.

关键词： fpga-based hardware architecture confidence detection adversarial attacks sensor pattern noise dnns

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DNNVM: End-to-End Compiler Leveraging Operation Fusion on fpga-based CNN Accelerators 19

DNNVM: End-to-End Compiler Leveraging Operation Fusion on FP...

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Yu Xing Shuang Liang Lingzhi Sui Zhen Zhang Jiantao Qiu Xijie Jia Xin Liu Yushun Wang Yi Shan Yu Wang Xilinx Beijing China Tsinghua University Beijing China

ISBN: (纸本)9781450361378

In recent years, Convolutional Neural Network(CNN) is becoming the state-of-the-art method in a wide range of Artificial Intelligence(AI) domains. The increasingly large and complex CNN models are both computation bound and I/O bound. fpga-based accelerators driven by custom Instruction Set Architecture(ISA) achieve a balance between generality and efficiency, and leave much room for optimization. Operation fusion which fuses adjacent operations without saving intermediate results back to off-chip DDR can greatly alleviate bandwidth pressure, operations can be executed by different computation engines concurrently for latency hiding. To leverage optimizations, especially operation fusion on custom instruction-based accelerators, we propose a full-stack compiler DNNVM(Deep Neural Network Virtual Machine). DNNVM is an integration of optimizers for framework-independent computing graph, loops and data layouts, an assembler, a runtime supporter and a validation environment. DNNVM works in the context of deep learning frameworks and transforms CNN models into a directed acyclic graph, XGraph. After analyzing the interaction among fusion depth, tiling across multiple stages and on-chip memory capacity, DNNVM enumerates all potentially profitable fusion opportunities according to custom fusion templates upon XGraph, by a subgraph isomorphism algorithm. In addition, DNNVM searches for the optimal execution strategies by a heuristic shortest-path algorithm. On Xilinx [email protected], we achieve up to 1.26x speedup than naïve implementations without fusion on GoogLeNet. On Xilinx [email protected], we achieve the throughput of 2.82 TOPs/s for VGG, 1.38 TOPs/s for ResNet50 - he fastest ever reported on comparable fpgas.

关键词： cnn operation fusion fpga-based accelerator compiler

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Vicilogic 2.0: Online Learning and Prototyping of Digital Systems Using PYNQ-Z1/-Z2 SoC 29

Vicilogic 2.0: Online Learning and Prototyping of Digital Sy...

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29th international symposium on Rapid System Prototyping, RSP 2018

作者： Morgan, Fearghal O'loughlin, Declan Audiger, Jeremy Boyer, Yohan Timlin-Canning, Niall Kepa, Krzysztof Cawley, Seamus Gallivan, Ian Bako, László Callaly, Frank National University of Ireland Galway Ireland Sapientia Hungarian University of Transylvania Romania

ISBN: (纸本)9781538675571

This paper presents viciLogic 2.0, a scalable, distributed online learning, hardware prototyping, client application and course creator platform for System on Chip (SoC)-based digital systems. User applications transparently link to a device in an array of Xilinx PYNQ-Zl or-Z2 SoC hardware in the cloud. The viciLogic prototype builder toolsuite (which integrates with the Xilinx Vivado industry-standard EDA tools) automates online (and local) SoC digital logic hardware prototyping, with integrated viciLogic user interface. The platform supports real-time user hardware input signal control and automated signal control, and probes the state of all user design internal and output signals. This enables the creation of responsive client applications and smart browser-based courses. Online course functions include guided lessons, SoC signal state monitoring for automatic course progression, knowledge checks, and user sandbox. The prototype builder uses source VHDL or Verilog projects created, simulated and synthesised in Vivado. The builder parses and modifies the HDL model to provide signal observability, integrates SoC resources (ARM, AXI interconnect, peripherals and viciLogic IP), and (using Vivado) generates the SoC hardware configuration bitstream and design metadata. The paper describes the viciLogic 2.0 server architecture, SoC prototype builder tool flow, client application creator, and online course creator. Two demonstration applications are presented, a counter course lesson step and a client application (16-bit single cycle computer, with IDE). © 2018 IEEE.

关键词： field programmable gate arrays (fpga)

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