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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是351-360 订阅

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Evaluating and Enhancing Intel® Stratix® 10 fpgas for Persistent Real-Time AI 19

Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Pers...

引用

Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Eriko Nurvitadhi Dongup Kwon Ali Jafari Andrew Boutros Jaewoong Sim Phillip Tomson Huseyin Sumbul Gregory Chen Phil Knag Raghavan Kumar Ram Krishnamurthy Debbie Marr Sergey Gribok Bogdan Pasca Martin Langhammer Aravind Dasu Intel Corporation Hillsboro OR USA Intel Corporation San Jose CA USA Intel Corporation France France Intel Corporation United Kingdom United Kingdom

ISBN: (纸本)9781450361378

Interactive intelligent services (e.g., smart web search) are becoming essential datacenter workloads. They rely on data-intensive artificial intelligence (AI) algorithms that do not use batch computation due to their tight latency constraints. Since off-chip data accesses have higher latency and energy consumption than on-chip accesses, a persistent AI approach with the entire model stored in on-chip memory is becoming the new norm for real-time AI. This approach is the cornerstone of Microsoft's Brainwave fpga-based AI cloud and was recently added to Nvidia's cuDNN library. In this work, we implement, optimize and evaluate a Brainwave-like neural processing unit (NPU) on a large Stratix-10 fpga. We benchmark it against a large Nvidia Volta GPU running cuDNN persistent AI kernels. Across real-time persistent RNN, GRU, and LSTM workloads, we show that Stratix-10 offers ~3× (FP32) and ~10× (INT8) better latency than GPU (FP32), which uses only ~6% of its peak throughput. Then, we propose TensorRAM, an ASIC chiplet for persistent AI that is 2.5D integrated with an fpga in the same package. TensorRAM enhances the on-chip memory capacity and bandwidth, with enough multi-precision INT8/4/2/1 throughput to match that bandwidth. Multiple TensorRAMs can be integrated with Stratix-10. Our evaluation shows that a small 32-mm2 TensorRAM on 10nm offers 64MB of SRAMs with 32TB/s on-chiplet bandwidth and 64 TOP/s (INT8). A small Stratix-10 with a TensorRAM (INT8) offers 16× better latency and 34× energy efficiency compared to GPU (FP32). Overall, Stratix-10 with TensorRAM offers compelling and scalable persistent AI solutions.

关键词： deep learning gpu ai fpga real-time asic

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Overcoming Data Transfer Bottlenecks in DNN Accelerators via Layer-Conscious Memory Managment 19

Overcoming Data Transfer Bottlenecks in DNN Accelerators via...

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Proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Xuechao Wei Yun Liang Peng Zhang Cody Hao Yu Jason Cong Peking University & Falcon Computing Solutions Inc. Beijing China Peking University Beijing China Falcon Computing Solutions Inc. Los Angeles CA USA University of California Los Angeles Los Angeles CA USA Peking University University of California Los Angeles & Falcon Computing Solutions Inc. Los Angeles CA USA

ISBN: (纸本)9781450361378

Deep Neural Networks (DNNs) are rapidly evolving to satisfy the performance and accuracy requirements in many real world applications. The evolution renders DNNs more and more complex in terms of network topology, data sizes and layer types. Currently most state-of-the-art DNN accelerators adopt a uniform memory hierarchy (UMH) design methodology, which means that the data transferring of all convolutional and fully connected layers must go through the same memory levels. Unfortunately, for some layers, the performance is always bounded by off-chip memory transferring. It is caused by the saturating of data reuse happening in on-chip buffers, resulting in underutilization of on-chip memory. To address this issue, we propose a layer-conscious memory hierarchy (LCMH) methodology for DNN accelerators. LCMH could determine the memory levels of all the layers according to their requirements for off-chip memory bandwidth and on-chip buffer size for the data sources. As a result, the off-chip memory footprints of memory bounded layers could be avoided by keeping the data of them on chip. In addition, we provide architectural support for the accelerators equipped with LCMH. Experimental results show that designs with layer- conscious memory management could achieve up to 36% speedup compared with the designs wth UMH and 5% improvement over state-of-the-art designs.

关键词： accelerator memory management dnns fpga

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Secure Function Evaluation Using an fpga Overlay Architecture 17

Secure Function Evaluation Using an FPGA Overlay Architectur...

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acm/sigda international symposium on field-programmable gate arrays

作者： Fang, Xin Ioannidis, Stratis Leeser, Miriam Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA

ISBN: (纸本)9781450343541

Secure Function Evaluation (SFE) has received considerable attention recently due to the massive collection and mining of personal data over the Internet, but large computational costs still render it impractical. In this paper, we leverage hardware acceleration to tackle the scalability and efficiency challenges inherent in SFE. To that end, we propose a generic, reconfigurable implementation of SFE as a coarse-grained fpga overlay architecture. Contrary to tailored approaches that are tied to the execution of a specific SFE structure, and require full reprogramming of an fpga with each new execution, our design allows repurposing an fpga to evaluate different SFE tasks without the need for reprogramming. Our implementation shows orders of magnitude improvement over a software package for evaluating garbled circuits, and demonstrates that the circuit being evaluated can change with almost no overhead.

关键词： fpga Secure Function Evaluation Garbled Circuits

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fpga Acceleration for Computational Glass-Free Displays 17

FPGA Acceleration for Computational Glass-Free Displays

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acm/sigda international symposium on field-programmable gate arrays

作者： He, Zhuolun Luo, Guojie Peking Univ Sch EECS Ctr Energy Efficient Comp & Applicat Beijing Peoples R China NUDT Collaborat Innovat Ctr High Performance Comp Changsha Hunan Peoples R China PKU UCLA Joint Res Inst Sci & Engn Beijing Peoples R China

ISBN: (纸本)9781450343541

The increasing computational power enables various new applications that are runtime prohibitive before. fpga is one of such computational power with both reconfigurability and energy efficiency. In this paper, we demonstrate the feasibility of eyeglasses-free displays through fpga acceleration. Specifically, we propose several techniques to accelerate the sparse matrix-vector multiplication and the L-BFGS iterative optimization algorithm with the consideration of the characteristics of fpgas. The experimental results show that we reach a 12.78X overall speedup of the glass-free display application.

关键词： fpga accelerator l-bfgs algorithm sparse matrix-vector multiplication light field display

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Synchronization Constraints for Interconnect Synthesis 17

Synchronization Constraints for Interconnect Synthesis

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acm/sigda international symposium on field-programmable gate arrays

作者： Rodionov, Alex Rose, Jonathan Univ Toronto Edward S Rogers Sr Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9781450343541

Interconnect synthesis tools ease the burden on the designer by automatically generating and optimizing communication hardware. In this paper we propose a novel capability for fpga interconnect synthesis tools that further simplifies the designer's effort: automatic cycle-level synchronization of data delivery. This capability enables the creation of interconnect with significantly reduced hardware cost, provided that communicating modules have fixed latency and do not apply upstream backpressure. To do so, the designer specifies constraints on the lengths, in clock cycles, of multi-hop logical communication paths. The tool then uses an integer programming-based method to insert balancing registers into optimal locations, satisfying the designer's constraints while minimizing register usage. On an example convolutional neural network application, the new approach uses 43% less area than a FIFO-based synchronization scheme.

关键词： Convolutional Neural Networks fpga Interconnect Synthesis

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120-core microAptiv MIPS Overlay for the Terasic DE5-NET fpga board 17

120-core microAptiv MIPS Overlay for the Terasic DE5-NET FPG...

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acm/sigda international symposium on field-programmable gate arrays

作者： Kumar, Chethan H. B. Ravi, Prashant Modi, Gourav Kapre, Nachiket Nanyang Technol Univ Sch Comp Sci & Engn Singapore Singapore Univ Waterloo Elect & Comp Engn Waterloo ON Canada

ISBN: (纸本)9781450343541

We design a 120-core 94 MHz MIPS processor fpga overlay interconnected with a lightweight message-passing fabric that fits on a Stratix V GX fpga (5SGXEA7N2F45C2). We use silicon-tested RTL source code for the microAptiv MIPS processor made available under the Imagination Technologies Academic Program. We augment the processor with suitable custom instruction extensions for moving data between the cores via explicit message passing. We support these instructions with a communication scratchpad that is optimized for high throughput injection of network traffic. We also demonstrate an end-to-end proof-of-concept flow that compiles C code with suitable MIPS UDI-supported (user-defined instructions) message passing workloads and stress-test with synthetic workloads.

关键词： miscellaneous

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Optimizations of Sequence Alignment on fpga: A Case Study of Extended Sequence Alignment (Abstact Only) 18

Optimizations of Sequence Alignment on FPGA: A Case Study of...

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Proceedings of the 2018 acm/sigda international symposium on field-programmable gate arrays

作者： Zheming Jin Kazutomo Yoshii Argonne National Laboratory Argonne USA Argonne National Laboratory Argonne USA

ISBN: (纸本)9781450356145

Detecting similarities between sequences is an important part of Bioinformatics. In this poster, we explore the use of high-level synthesis tool and a field-programmable gate array (fpga) for optimizing a sequence alignment algorithm. We demonstrate the optimization techniques to improve the performance of the extended sequence alignment algorithm in the BWA software package, a tool for mapping DNA sequences against a large reference sequence. Applying the optimizations to the algorithm using Xilinx SDAccel OpenCL-to-fpga tool, we reduce the kernel execution time from 62.8 ms to 0.45 ms while the power consumption is approximately 11 Watts on the ADM-PCIE-8K5 fpga platform.

关键词： opencl fpga sequence alignment

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Automatic Construction of Program-Optimized fpga Memory Networks 17

Automatic Construction of Program-Optimized FPGA Memory Netw...

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acm/sigda international symposium on field-programmable gate arrays

作者： Yang, Hsin-Jung Fleming, Kermin Winterstein, Felix Chen, Annie I. Adler, Michael Emer, Joel MIT CSAIL 77 Massachusetts Ave Cambridge MA 02139 USA Intel Corp SSG Grp Santa Clara CA 95051 USA Imperial Coll London CAS Grp London England MIT EECS 77 Massachusetts Ave Cambridge MA 02139 USA

ISBN: (纸本)9781450343541

Memory systems play a key role in the performance of fpga applications. As fpga deployments move towards design entry points that are more serial, memory latency has become a serious design consideration. For these applications, memory network optimization is essential in improving performance. In this paper, we examine the automatic, program-optimized construction of low-latency memory networks. We design a feedback-driven network compiler, which constructs an optimized memory network based on the target program's memory access behavior measured via a newly designed network profiler. In our test applications, the compiler-optimized networks provide a 45% performance gain on average over baseline memory networks by minimizing the impact of network latency on program performance.

关键词： network on chip memory network fpga memory system reconfigurable computing compiler optimization

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fpga 2014 - Proceedings of the 2014 acm/sigda international symposium on field programmable gate arrays

FPGA 2014 - Proceedings of the 2014 ACM/SIGDA International ...

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2014 acm/sigda international symposium on field programmable gate arrays, fpga 2014

ISBN: (纸本)9781450326711

The proceedings contain 30 papers. The topics discussed include: fast and effective placement and routing directed high-level synthesis for fpgas;optimizing effective interconnect capacitance for fpga power reduction;towards interconnect-adaptive packing for fpgas;modular multi-ported SRAM-based memories;scalable multi-access flash store for big data analytics;cad and routing architecture for interposer-based multi-fpga systems;memory block based scan-BIST architecture for application-dependent fpga testing;fpga-based biophysically-meaningful modeling of olivocerebellar neurons;square-rich fixed point polynomial evaluation on fpgaS;a power side-channel-based digital to analog converter for Xilinx fpgas;MORP: MakeSpan optimization for processors with an embedded reconfigurable fabric;a scalable sparse matrix-vector multiplication kernel for energy-efficient sparse-BLAs on fpgas;and Wordwidth, instructions, looping, and virtualization: the role of sharing in absolute energy minimization.

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Don't Forget the Memory: Automatic Block RAM Modelling, Optimization, and Architecture Exploration 17

Don't Forget the Memory: Automatic Block RAM Modelling, Opti...

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acm/sigda international symposium on field-programmable gate arrays

作者： Yazdanshenas, Sadegh Tatsumura, Kosuke Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada Toshiba Co Ltd Corp R&D Ctr Adv LSI Technol Lab Tokyo Japan

ISBN: (纸本)9781450343541

While academic fpga architecture exploration tools have become sufficiently advanced to enable a wide variety of explorations and optimizations on soft fabric and routing, support for Block RAM (BRAM) has been very limited. In this paper, we present enhancements to the COFFE transistor sizing tool to facilitate automatic generation and optimization of BRAM for both SRAM and Magnetic Tunnelling Junction technologies. These new capabilities enable investigation of area, delay, and energy trends for various sizes of BRAM or different BRAM technologies. We also validate these trends against available commercial fpga BRAM data. Furthermore, we demonstrate that BRAMs generated by COFFE can be used to carry out system-level architecture explorations using an area-oriented RAM-mapping flow and the Verilog-To-Routing flow.

关键词： On-chip Memory fpga BRAM Automatic Transistor Sizing SRAM Magnetic Tunnelling Junction

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