检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,335 篇 会议
41 篇 期刊文献

馆藏范围

1,376 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

811 篇 工学
- 784 篇 计算机科学与技术...
- 348 篇 软件工程
- 281 篇 电气工程
- 259 篇 电子科学与技术（可...
- 122 篇 信息与通信工程
- 36 篇 动力工程及工程热...
- 35 篇 控制科学与工程
- 30 篇 机械工程
- 17 篇 生物工程
- 14 篇 仪器科学与技术
- 12 篇 建筑学
- 12 篇 土木工程
- 10 篇 生物医学工程（可授...
- 9 篇 冶金工程
- 8 篇 化学工程与技术
- 7 篇 光学工程
- 7 篇 材料科学与工程（可...
- 3 篇 农业工程
224 篇 理学
- 184 篇 数学
- 36 篇 物理学
- 20 篇 统计学（可授理学、...
- 19 篇 生物学
- 11 篇 系统科学
- 7 篇 化学
62 篇 管理学
- 50 篇 管理科学与工程(可...
- 34 篇 工商管理
- 13 篇 图书情报与档案管...
16 篇 经济学
- 16 篇 应用经济学
11 篇 法学
- 9 篇 社会学
3 篇 农学
- 3 篇 作物学
2 篇 教育学
1 篇 医学

主题

451 篇 fpga
269 篇 field programmab...
171 篇 field programmab...
27 篇 high-level synth...
26 篇 reconfigurable c...
22 篇 deep learning
22 篇 opencl
20 篇 computer archite...
18 篇 hls
18 篇 routing
18 篇 hardware acceler...
18 篇 hardware
17 篇 fpgas
16 篇 accelerator
16 篇 placement
14 篇 neural networks
14 篇 cnn
14 篇 machine learning
14 篇 convolutional ne...
13 篇 clocks

机构

19 篇 university of ca...
12 篇 tsinghua univers...
12 篇 fudan university
12 篇 imperial college...
11 篇 university of to...
10 篇 peking universit...
10 篇 university of to...
9 篇 university of ce...
9 篇 university of so...
8 篇 univ of californ...
7 篇 university of sc...
7 篇 univ of toronto ...
7 篇 epfl lausanne
7 篇 école polytechni...
7 篇 univ toronto dep...
7 篇 nanyang technolo...
7 篇 tsinghua univ pe...
6 篇 univ british col...
6 篇 univ calif los a...
6 篇 northeastern uni...

作者

37 篇 cong jason
26 篇 rose jonathan
22 篇 jason cong
17 篇 betz vaughn
15 篇 zhang zhiru
14 篇 chen deming
13 篇 ienne paolo
12 篇 chow paul
12 篇 wawrzynek john
11 篇 hauck scott
10 篇 dehon andré
10 篇 luk wayne
10 篇 prasanna viktor ...
10 篇 langhammer marti...
9 篇 jinmei lai
9 篇 anderson jason h...
9 篇 wilton steven j....
9 篇 schmit herman
9 篇 jonathan rose
9 篇 constantinides g...

语言

1,356 篇 英文
19 篇 其他
1 篇 中文

检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是401-410 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

A Low-power APUF-based Environmental Abnormality Detection Framework 22

A Low-power APUF-based Environmental Abnormality Detection F...

引用

22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Gu, Hongxiang Xu, Teng Potkonjak, Miodrag Univ Calif Los Angeles Comp Sci Dept Los Angeles CA 90095 USA

ISBN: (纸本)9781509060238

Physical unclonable functions (PUFs) take advantage of the effect of process variation on hardware to obtain their unclonability. Traditional PUF design only focuses on the analog signals of circuits. An arbiter PUF, for example, generates responses by racing delay signals. Implementations of such PUFs usually employ large area and power consumption while providing very low throughput. To address this problem, we propose an energy efficient PUF design in such a way that it races analog signals and computes digital logic simultaneously. More importantly, the analog portion of the circuit (racing) shares a large amount of hardware resources with the digital portion of the circuit (computing) by introducing only small overhead in terms of area and power. Our test results on Spartan-6 field-programmable gate array (fpga) platforms indicate that by combining the two outputs, our design enables much larger PUF output throughput, better randomness and less power consumption compared to traditional PUFs.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

来源：评论

学校读者我要写书评

暂无评论

Dynamic Partitioning for Library based Placement on Heterogeneous fpgas 17

Dynamic Partitioning for Library based Placement on Heteroge...

引用

acm/sigda international symposium on field-programmable gate arrays

作者： Mao, Fubing Zhang, Wei He, Bingsheng Lam, Siew-Kei Nanyang Technol Univ Singapore Singapore Hong Kong Univ Sci & Technol Hong Kong Peoples R China Natl Univ Singapore Singapore Singapore

ISBN: (纸本)9781450343541

Library based design and IP reuses have been previously proposed to speed up the synthesis of large-scale fpga designs. However, existing methods result in large area wastage due to the module size difference and the waste area inside each module. In this paper, we propose an efficient and dynamic module partitioning approach for the library based design flow that minimizes the area wastage. Our proposed approach efficiently utilizes the pre-placement module information such as relative positions of blocks including CLBs, DSPs and RAMs, and the module sizes (width, height) for placing these blocks. We introduce a B*-tree representation to enable a fast modular placement. Simulated annealing algorithm is adopted to direct each round of the placement and to search for the optimization. We develop a set of efficient rules to guide the module selection and partition during placement, to eliminate the waste area inside and between modules and achieve a more compact final placement. In addition, the proposed approach can adapt to different architectures and address the fixed-outline constraint. Experiment results show that our approach can reduce the fpga area utilization by up to 19% compared with the state-of-the-art approach while with acceptable runtime. More detailed description of this poster can be found in our technical report [1].

关键词： fpga B*-tree Placement Dynamic Partitioning

来源：评论

学校读者我要写书评

暂无评论

A Batch Normalization Free Binarized Convolutional Deep Neural Network on an fpga 17

A Batch Normalization Free Binarized Convolutional Deep Neur...

引用

acm/sigda international symposium on field-programmable gate arrays

作者： Nakahara, Hiroki Yonekawa, Haruyoshi Iwamoto, Hisashi Motomura, Masato Tokyo Inst Technol Tokyo Japan Poco A Poco Networks Osaka Japan Hokkaido Univ Sapporo Hokkaido Japan

ISBN: (纸本)9781450343541

A pre-trained convolutional deep neural network (CNN) is a feed-forward computation perspective, which is widely used for the embedded systems, requires high power-and-area efficiency. This paper realizes a binarized CNN which treats only binary 2-values (+1/-1) for the inputs and the weights. In this case, the multiplier is replaced into an XNOR circuit instead of a dedicated DSP block. For hardware implementation, using binarized inputs and weights is more suitable. However, the binarized CNN requires the batch normalization techniques to retain the classification accuracy. In that case, the additional multiplication and addition require extra hardware, also, the memory access for its parameters reduces system performance. In this paper, we propose the batch normalization free CNN which is mathematically equivalent to the CNN using batch normalization. The proposed CNN treats the binarized inputs and weights with the integer bias. We implemented the VGG-16 benchmark CNN on the Netfpga-SUME fpga board, which has the Xilinx Inc. Virtex7 fpga and three off-chip QDR II+ Synchronous SRAMs. Compared with the conventional fpga realizations, although the classification error rate is 6.5% decayed, the performance is 2.82 times faster, the power efficiency is 1.76 times lower, and the area efficiency is 11.03 times smaller. Thus, our method is suitable for the embedded computer system.

关键词： Binarized Deep Neural Network fpga

来源：评论

学校读者我要写书评

暂无评论

High-Throughput Lossless Compression on Tightly Coupled CPU-fpga Platforms: (Abstract Only) 18

High-Throughput Lossless Compression on Tightly Coupled CPU-...

引用

Proceedings of the 2018 acm/sigda international symposium on field-programmable gate arrays

作者： Weikang Qiao Jieqiong Du Zhenman Fang Libo Wang Michael Lo Mau-Chung Frank Chang Jason Cong University of California Los Angeles Los Angeles CA USA

ISBN: (纸本)9781450356145

Data compression techniques have been widely used to reduce the data storage and movement overhead, especially in the big data era. Recent studies demonstrate the great promise of fpgas to improve the throughput of lossless compression algorithms that are very computation-intensive. However, when such fpga-based compression accelerators are integrated with the processors, the overall system throughput is typically limited by the communication between a CPU and an fpga. This study proposes a novel scheme to achieve high-throughput lossless compression on modern Intel-Altera HARPv2 platforms, where a Xeon CPU and an Altera fpga are tightly coupled to improve the CPU-fpga communication. First, it implements a multi-way parallel and fully pipelined compression accelerator based on Deflate algorithm. The accelerator itself can achieve a maximum throughput of 12.8 GB/s and a compression ratio of 2.03 over standard benchmarks. In addition, various trade-offs among compression throughput, compression ratio, fpga resource utilization and scalability are explored to optimize the accelerator design based on different application requirements. Moreover, this study exploits the high CPU-fpga communication bandwidth of HARPv2 platforms to improve the compression throughput of the overall system, which can achieve an average practical end-to-end throughput of 10.0 GB/s (up to 12 GB/s for larger input files) on HARPv2.

关键词： end-to-end communication bandwidth deflate lossless compression

来源：评论

学校读者我要写书评

暂无评论

Measuring the Power-Constrained Performance and Energy Gap between fpgas and Processors 17

Measuring the Power-Constrained Performance and Energy Gap b...

引用

acm/sigda international symposium on field-programmable gate arrays

作者： Ye, Andy Gean Ganesan, Karthik Ryerson Univ Toronto ON Canada Univ Toronto Toronto ON Canada

ISBN: (纸本)9781450343541

This work measures the performance and power consumption gap between the current generation of low power fpgas and low power microprocessors (microcontrollers) through an implementation of the Canny edge detection algorithm. In particular, the algorithm is implemented on Altera MAX 10 fpgas and its performance and power consumption are then compared to the same algorithm implemented on the STMicroelectronics' implementation of the ARM M-series microcontrollers. We found an extremely high, four- to five-orders of magnitude, performance advantage of the fpgas over the microcontrollers, which is much greater than any previously reported values in fpgas vs. processors studies. Furthermore, this speedup only comes at a cost of 1.2x to 15x higher power consumption, which gives fpgas a significant advantage in energy efficiency. We also observe, however, the current generation of low power fpgas have significantly higher static power consumption than the microcontrollers. In particular, the low power fpgas consume more static power than the total power consumption of the lowest power consuming microcontrollers, rendering the fpgas inoperable under the power budgets of these processors. Furthermore, this high static power consumption exists despite the fact that the fpgas are implemented on a low leakage 55nm process with dual supply voltages while the microcontrollers are implemented on a conventional, single supply voltage, 90nm process. Consequently, our results indicate that it is particular important for future research to address the static power consumption of low power fpgas while maintaining logic capacity so the performance and energy efficiency advantages of the fpgas can be fully utilized in the extremely low power application domain that are driven by batteries with very small form factors and emerging small scale energy harvesting technologies.

关键词： field programmable gate arrays (fpgas) Low-Power fpgas fpga vs. Microcontroller Performance Energy Efficiency

来源：评论

学校读者我要写书评

暂无评论

A fpga Friendly Approximate Computing Framework with Hybrid Neural Networks: (Abstract Only) 18

A FPGA Friendly Approximate Computing Framework with Hybrid ...

引用

Proceedings of the 2018 acm/sigda international symposium on field-programmable gate arrays

作者： Haiyue Song Xiang Song Tianjian Li Hao Dong Naifeng Jing Xiaoyao Liang Li Jiang Shanghai Jiao Tong University Shanghai China

ISBN: (纸本)9781450356145

Neural approximate computing is promising to gain energy-efficiency at the cost of tolerable quality loss. The architecture contains two neural networks: the approximate accelerator generates approximate results while the classifier determines whether input data can be safely approximated. However, they are not compatible to a heterogeneous computing platform, due to the large communication overhead between the approximate accelerator and accurate cores, and the large speed gap between them. This paper proposes a software-hardware co-design strategy. With deep exploration of data distributions in the feature space, we first propose a novel approximate computing architecture containing a multi-class classifier and multiple approximate accelerator; this architecture, derived by the existing iterative co-training methods, can shift more data from accurate computation (in CPU) to approximate accelerator (in fpga); the increased invocation of the approximate accelerator thus can yield higher utilization of the fpga-based accelerator, resulting in the enhanced the performance. Moreover, much less input data is redistributed, by the classifier (also in fpga), back to CPU, which can minimize the CPU-fpga communication. Second, we design a pipelined data-path with batched input/output for the proposed hybrid architecture to efficiently hide the communication latency. A mask technique is proposed to decouple the synchronization between CPU and fpga, in order to minimize the frequency of communication.

关键词： neural network fpga approximate computing

来源：评论

学校读者我要写书评

暂无评论

CPU-fpga Co-Optimization for Big Data Applications: A Case Study of In-Memory Samtool Sorting 17

CPU-FPGA Co-Optimization for Big Data Applications: A Case S...

引用

acm/sigda international symposium on field-programmable gate arrays

作者： Cong, Jason Fang, Zhenman Huang, Muhuan Wang, Libo Wu, Di Univ Calif Los Angeles Los Angeles CA 90024 USA

ISBN: (纸本)9781450343541

To efficiently process a tremendous amount of data, today's big data applications tend to distribute the datasets into multiple partitions, such that each partition can be fit into memory and be processed by a separate core/server in parallel. Meanwhile, due to the limited scaling of general-purpose CPUs, fpgas have emerged as an attractive alternative to accelerate big data applications due to their low power, high performance and energy efficiency. In this paper we aim to answer one key question: How should the multicore CPU and fpga coordinate together to optimize the performance of big data applications? To address the above question, we conduct a step-by-step case study to perform CPU and fpga co-optimization for in-memory Samtool sorting in genomic data processing, which is one of the most important big data applications for personalized healthcare. First, to accelerate the time-consuming compression algorithm and its associated cyclic redundancy check (CRC) in Samtool sorting, we implement a portable and maintainable fpga accelerator using high-level synthesis (HLS). Although fpgas are traditionally well-known to be suitable for compression and CRC, we find that a straightforward integration of this fpga accelerator into the multi-threaded Samtool sorting only achieves marginal system throughput improvement over the software baseline running on a 12-core CPU. To improve system performance, we propose a dataflow execution model to effectively orchestrate the computation between the multi-threaded CPU and fpga. Experimental results show that our co-optimized CPU-fpga system achieves a 2.6x speedup for in-memory Samtool sorting.

关键词： Compression and CRC Genome data sorting Dataflow execution

来源：评论

学校读者我要写书评

暂无评论

K-Flow: A Programming and Scheduling Framework to Optimize Dataflow Execution on CPU-fpga Platforms: (Abstract Only) 18

K-Flow: A Programming and Scheduling Framework to Optimize D...

引用

Proceedings of the 2018 acm/sigda international symposium on field-programmable gate arrays

作者： Jason Cong Zhenman Fang Yao Hu Di Wu University of California Los Angeles Los Angeles CA USA Xilinx Inc. & University of California Los Angeles San Jose CA USA Falcon Computing Solutions Inc. Santa Clara CA USA

ISBN: (纸本)9781450356145

With the slowing down of Moore's law, major cloud service providers---such as Amazon Web Services, Microsoft Azure, and Alibaba Cloud---all started deploying fpgas in their cloud platforms to improve the performance and energy-efficiency. From the perspective of performance per unit cost in the cloud, it is essential to efficiently utilize all available CPU and fpga resources within a requested computing instance. However, most prior studies overlook the CPU-fpga co-optimization or require a considerable amount of manual efforts to achieve it. In this poster, we present a framework called K-Flow, which enables easy fpga accelerator integration and efficient CPU-fpga co-scheduling for big data applications. K-Flow abstracts an application as a widely used directed acyclic graph (DAG), and dynamically schedules a number of CPU threads and/or fpga accelerator processing elements (PEs) to execute the dataflow tasks on each DAG node. Moreover, K-Flow provides user-friendly interfaces to program each DAG node and automates the tedious process of fpga accelerator integration and CPU-fpga co-optimization using the genomic read alignment application BWA-MEM as a case study. Experimental results show that K-Flow achieves a throughput that is on average 94.5% of the theoretical upper bound and 1.4x better than a straightforward fpga integration.

关键词： fpga in the cloud dataflow programming genomic sequences alignment fpga/cpu co-execution

来源：评论

学校读者我要写书评

暂无评论

Accelerating Financial Market Server through Hybrid List Design 17

Accelerating Financial Market Server through Hybrid List Des...

引用

acm/sigda international symposium on field-programmable gate arrays

作者： Fu, Haohuan He, Conghui Ruan, Huabin Greenspon, Itay Luk, Wayne Zheng, Yongkang Liao, Junfeng Zhang, Qing Yang, Guangwen Tsinghua Univ Beijing Peoples R China Maxeler Technol London England Imperial Coll London London England China Financial Futures Exchange Shanghai Peoples R China

ISBN: (纸本)9781450343541

The financial market server in exchanges aims to maintain the order books and provide real time market data feeds to traders. Low-latency processing is in a great demand in financial trading. Although software solutions provide the flexibility to express algorithms in high-level programming models and to recompile quickly, it is becoming increasingly uncompetitive due to the long and unpredictable response time. Nowadays, field programmable gate arrays (fpgas) have been proved to be an established technology for achieving a low and constant latency for processing streaming packets in a hardware accelerated way. However, maintaining order books on fpgas involves organizing packets into GBs of structural data information as well as complicated routines (sort, insertion, deletion, etc.), which is extremely challenging to fpga designs in both design methodology and memory volume. Thus existing fpga designs often leave the post-processing part to the CPUs. However, it largely cancels the latency gain of the network packet processing part. This paper proposes a CPU-fpga hybrid list design to accelerate financial market servers that achieve microsecond-level latencies. This paper mainly includes four contributions. First, we design a CPU-fpga hybrid list with two levels, a small cache list on the fpga and a large master list at the CPU host. Both lists are sorted with different sorting schemes, where the bitonic sort is applied to the cache list while a balanced tree is used to maintain the master list. Second, in order to effectively update the hybrid sorted list, we derive a complete set of low-latency routines, including insertion, deletion, selection, sorting, etc., providing a low latency at the scale of a few cycles. Third, we propose a non-blocking on-demand synchronization strategy for the cache list and the master list to communicate with each other. Lastly, we integrate the hybrid list as well as other components, such as packets splitting, parsing, processing, e

关键词： fpga low latency database market server finance

来源：评论

学校读者我要写书评

暂无评论

fpga 2017 chairs' welcome

FPGA 2017 - Proceedings of the 2017 ACM/SIGDA International ...

引用

fpga 2017 - Proceedings of the 2017 acm/sigda international symposium on field-programmable gate arrays 2017年 iii页

作者： Anderson, Jason H. Greene, Jonathan University of Toronto Canada Microsemi United States

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共138页 << < 37 38 39 40 41 42 43 44 45 46 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：