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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是411-420 订阅

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A Framework for Iterative Stencil Algorithm Synthesis on fpgas from OpenCL Programming Model 17

A Framework for Iterative Stencil Algorithm Synthesis on FPG...

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acm/sigda international symposium on field-programmable gate arrays

作者： Wang, Shuo Liang, Yun Peking Univ Beijing Peoples R China

ISBN: (纸本)9781450343541

Iterative stencil algorithms find applications in a wide range of domains. fpgas have long been adopted for computation acceleration due to its advantages of dedicated hardware design. Hence, fpgas are a compelling alternative for executing iterative stencil algorithms. However, efficient implementation of iterative stencil algorithms on fpgas is very challenging due to the data dependencies between iterations and elements in the stencil algorithms, programming hurdle of fpgas, and large design space. In this paper, we present a comprehensive framework that synthesizes iterative stencil algorithms on fpgas efficiently. We leverage the OpenCL-to-fpga tool chain to generate accelerator automatically and perform design space exploration at high level. We propose to bridge the neighboring tiles through pipe and enable data sharing among them to improve computation efficiency. We first propose a homogeneous design with equal tile size. Then, we extend to a heterogeneous design with different tile size to balance the computation among different tiles. Our designs exhibit a large design space in terms of tile structure. We also develop analytical performance models to explore the complex design space. Experiments using a wide range of stencil applications demonstrate that on average our homogeneous and heterogeneous implementations achieve 1.49X and 1.65X performance speedup respectively but with less hardware resource compared to the state-of-the-art.

关键词： Stencil fpga OpenCL

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FastTrack: Exploiting Fast fpga Wiring for Implementing NoC Shortcuts (Abstract Only) 18

FastTrack: Exploiting Fast FPGA Wiring for Implementing NoC ...

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Proceedings of the 2018 acm/sigda international symposium on field-programmable gate arrays

作者： Nachiket Kapre Tushar Krishna University of Waterloo Waterloo ON Canada Georgia Tech Atlanta GA USA

ISBN: (纸本)9781450356145

The latency of packet-switched fpga overlay Networks-on-Chip (NoCs) goes up linearly with the NoC dimensions, since packets typically spend a cycle in each dynamic router along the path. High-performance fpga NoCs have to aggressively pipeline interconnects, thereby adding extra latency overhead to the NoC. The use of fpga-friendly deflection routing schemes further exacerbates latency. Fortunately, fpgas provide segmented interconnects with different lengths (speeds). Faster fpga tracks can be used to reduce the number of switchbox hops along the packet path. We introduce FastTrack, an adaption to the NoC organization that inserts express bypass links in the NoC to skip multiple router stages in a single clock cycle. Our FastTrack design can be tuned to support different express link lengths for performance, and depopulation strategies for controlling cost. For the Xilinx Virtex-7 485T fpga, an 8×8 FastTrack NoC is 2× larger than a base Hoplite NoC, but operates between 1.2-0.8× its clock frequency when using express links of length 2-4. FastTrack delivers throughput and latency improvements across a range of statistical workloads (2-2.5×), and traces extracted from fpga accelerator case studies such as Sparse Matrix-Vector Multiplication (2.5×), Graph Analytics (2.8×), and Multi-processor overlay applications (2×). FastTrack also shows energy efficiency improvements by factors of up to 2× over baseline Hoplite due to higher sustained rates and high speed operation of express links made possible by fast fpga interconnect.

关键词： high-radix routers network-on-chip fpga overlay noc

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GRT 2.0: An fpga-based SDR Platform for Cognitive Radio Networks 17

GRT 2.0: An FPGA-based SDR Platform for Cognitive Radio Netw...

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acm/sigda international symposium on field-programmable gate arrays

作者： Wu, Haoyang Wang, Tao Li, Zhiwei Ding, Boyan Li, Xiaoguang Jiang, Tianfu Liu, Jun Lu, Songwu Peking Univ Beijing Peoples R China Univ Calif Los Angeles Los Angeles CA USA

ISBN: (纸本)9781450343541

Although there is explosive growth of theoretical research on cognitive radio, the real-time platform for cognitive radio is progressing at a low pace. Researchers expect fast prototyping their designs with appropriate wireless platforms to precisely evaluate and validate their new designs. Platforms for cognitive radio should provide both high-performance and programmability. We observed that for the parallel and reconfigurable nature, fpga is suitable for developing real-time software-defined radio (SDR) platforms. However, without a carefully designed "middleware architecture layer", Real-time programmable wireless system is still difficult to build. In this paper, we present GRT 2.0, a novel high-performance and programmable SDR platform for cognitive radio. This paper focuses on the architecture design of media access control (MAC) layer and radio frequency (RF) front-end interface. We allocate different MAC functions into different computing units, including a dedicated, light-weight embedded processor and several peripherals, to ensure both programmability and microsecond-level timing requirements. A serial-to-parallel converter is adopted to solve the issues of frame type matching and precise timing between PHY and RF. To support mobile host computers, we use the more portable USB 3.0 interface instead of PCIe. Finally, with the design of an efficient "gain lock" state machine, automatic gain control (AGC) processing time has been reduced to less than 1us. The evaluation result shows that with 802.11a/g protocol, GRT 2.0 achieves maximum throughput of 23Mbps in MAC, which is compatible to commodity fixed-logic wireless network adaptors. The latency of RF front-end is less than 2us, over 10X performance improvement to the Ethernet cable interface. Moreover, by carefully designed "middleware architecture layer" in fpga, we provide good programmability both in MAC and PHY.

关键词： Software Defined Radio Cognitive Radio fpga Wireless

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fpgas in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort (pHS5)(Abstract Only) 18

FPGAs in the Datacenters: the Case of Parallel Hybrid Super ...

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Proceedings of the 2018 acm/sigda international symposium on field-programmable gate arrays

作者： Mikhail Asiatici Damian Maiorano Paolo Ienne École Polytechnique Fédérale de Lausanne (EPFL) Lausanne Switzerland Politecnico di Torino Torino Italy

ISBN: (纸本)9781450356145

String sorting is an important part of database and MapReduce applications; however, it has not been studied as extensively as sorting of fixed-length keys. Handling variable-length keys in hardware is challenging and it is no surprise that no string sorters on fpga have been proposed yet. We present Parallel Hybrid Super Scalar String Sample Sort (pHS5) on Intel HARPv2, a heterogeneous CPU-fpga system with a server-grade multi-core CPU. Our pHS5 is based on the state-of-the-art string sorting algorithm for multi-core shared memory CPUs, pS5, which we extended with multiple processing elements (PEs) on the fpga. Each PE accelerates one instance of the most effectively parallelizable dominant kernel of pS5 by up to 33% compared to a single Intel Xeon Broadwell core running at 3.4 GHz. Furthermore, we extended the job scheduling mechanism of pS5 to enable our PEs to compete with the CPU cores for processing the accelerable kernel, while retaining the complex high-level control flow and the sorting of the smaller data sets on the CPU. We accelerate the whole algorithm by up to 10% compared to the 28 thread software baseline running on the 14-core Xeon processor and by up to 36% at lower thread counts.

关键词： heterogeneous computing fpga string sorting

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Software-Defined fpga-Based Accelerator for Deep Convolutional Neural Networks: (Abstract Only) 18

Software-Defined FPGA-Based Accelerator for Deep Convolution...

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Proceedings of the 2018 acm/sigda international symposium on field-programmable gate arrays

作者： Yankang Du Qinrang Liu Shuai Wei Chen Gao National Digital Switching System Engineering & Technology Research Center ZhengZhou China

ISBN: (纸本)9781450356145

Now, Convolutional Neural Network (CNN) has gained great popularity. Intensive computation and huge external data access amount are two challenged factors for the hardware acceleration. Besides these, the ability to deal with various CNN models is also challenged. At present, most of the proposed fpga-based CNN accelerator either can only deal with specific CNN models or should be re-coded and re-download on the fpga for the different CNN models. This would bring great trouble for the developers. In this paper, we designed a software-defined architecture to cope with different CNN models while keeping high throughput. The hardware can be programmed according to the requirement. Several techniques are proposed to optimize the performance of our accelerators. For the convolutional layer, we proposed the software-defined data reuse technique to ensure that all the parameters can be only loaded once during the computing phase. This will reduce large off-chip data access amount and the need for the memory and the need for the memory bandwidth. By using the sparse property of the input feature map, almost 80% weight parameters can be skipped to be loaded in the full-connected (FC) layer. Compared to the previous works, our software-defined accelerator has the highest flexibility while keeping relative high throughout. Besides this, our accelerator also has lower off-chip data access amount which has a great effect on the power consumption.

关键词： accelerator cnn fpga software-defined

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ASAP: Accelerated Short Read Alignment on programmable Hardware 17

ASAP: Accelerated Short Read Alignment on Programmable Hardw...

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acm/sigda international symposium on field-programmable gate arrays

作者： Banerjee, Subho S. el-Hadedy, Mohamed Lim, Jong B. Chen, Daniel Kalbarczyk, Zbigniew T. Chen, Deming Iyer, Ravishankar K. Univ Illinois Champaign IL USA

ISBN: (纸本)9781450343541

The proliferation of high-throughput sequencing machines allows for the rapid generation of billions of short nucleotide fragments in a short period. This massive amount of sequence data can quickly overwhelm today's storage and compute infrastructure. This poster explores the use of hardware acceleration to significantly improve the runtime of short-read alignment (SRA), a crucial step in pre-processing sequenced genomes. It presents the design and implementation of ASAP, an accelerator for computing Levenshtein distance (LD) in the context of the SRA problem. LD computation is a prominent underlying mathematical kernel that is common to a large number of SRA tools (e.g., BLAST, BWA, SNAP) and is responsible for 50-70% of their runtime. These algorithms mentioned above calculate the exact value of LD between nucleotide strings but only use them to build a total ordering (an ordered list) of the most likely point of origin in the genome. ASAP computes an approximation of LD by encoding computation in propagation delay of circuit elements. This approximation is calculated in an accelerated fashion in hardware and preserves the original total ordering of LDs produced by the traditional algorithms. This computation is performed by constructing circuits that comprise the recursive definition of the LD computation and measuring propagation delay of a signal entering and leaving the circuit. Additionally, ASAP can explore large portions of the search space (substrings of the strings being compared) within one clock cycle, and ignore parts of the search space that does not contribute to an answer. Our design is implemented on an Altera Stratix V fpga in an IBM POWER8 system using the CAPI interface for cache coherence across the CPU and fpga. Our design is 200x faster (median measurement) than the equivalent C implementation of the kernel running on the host processor and 2.2x faster for an end-to-end alignment tool for 120-150bp short-read sequences.

关键词： fpga Bioinformatics Genomics

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FGC: A Tool-flow for Generating and Configuring Custom fpgas(Abstract Only) 18

FGC: A Tool-flow for Generating and Configuring Custom FPGAs...

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Proceedings of the 2018 acm/sigda international symposium on field-programmable gate arrays

作者： Oluseyi A. Ayorinde He Qi Benton H. Calhoun US Army Research Lab - West (LA) Los Angeles CA USA University of Virginia Charlottesville VA USA

ISBN: (纸本)9781450356145

We introduce the FGC Toolflow, the only tool providing flexible custom-fpga generation and configuration to-date. Currently, researchers building custom fpgas must create for fpga schematics and bitstreams by hand. Both tasks are prohibitively time intensive and error prone. Additionally, the simulation time for bitcell configuration is very long (often times longer than the functionality), making the verification of fpga fabrics even more time consuming. Some existing toolflows and software packages designed to help with this process, but they only generate bitcell configurations, leaving schematics to be developed by hand. Others have limitations in circuit-level and architectural parameters, which prevent them from adequately exploring the fpga design space. The FGC flow is the only flow available that generates a custom full-fpga schematic from a single parameter text file, and generates the proper configuration bitstream for a target Verilog functionality. The parameter text file can accommodate 100s of different parameters, which include both circuit-level and architectural parameters to fully encompass the fpga design space. The FGC flow generates both a schematic and a configuration bitstream for an fpga with 100 CLBs (900,000 transistors) in only 8 minutes. The flow also generates simulation files, allowing the user to quickly set up and perform simulations to verify the fpga and its configuration at the chip level with SPICE-level accuracy. This flow was used to create, verify, and test a taped-out ultra-low power fpga.

关键词： automation cad for fpgas bitstream generation custom fpga generation design space exploration simulation

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A Self-adaptation Method of Fitting Convolutional Neural Network into fpga: Abstract Only) 18

A Self-adaptation Method of Fitting Convolutional Neural Net...

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Proceedings of the 2018 acm/sigda international symposium on field-programmable gate arrays

作者： Ning Mao Zhihong Huang Xing Wei He Zhao Xinkai Di Le Yu Haigang Yang Institute of Electronics Chinese Academy of Sciences & University of Chinese Academy of Sciences Beijing China Beijing Technology and Business University Beijing China

ISBN: (纸本)9781450356145

In recent years, Convolutional Neural Networks (CNNs) have been used widely in many artificial intelligence (AI) related fields. Of many implementation platforms for CNNs, fpga is regarded as an optimal platform because of its high power-efficiency and flexibility. Although various fpga accelerators have been proposed to realize CNN, some of them are implemented by High-Level Synthesis such as in OpenCL. This may result in inefficiency in operation performance and resource utilization. Therefore, we propose to parameterize the RTL design at both algorithm and hardware implementation levels. Four types of parallelism are considered to model the parameterized design in terms of the input feature map, the output feature map, the layer and the convolution kernel. Meanwhile a library covering convolution layer, fully-connected layer, pooling layer, control module is established to cater for various CNN models. Further, an algorithm is proposed to find an optimal level of parallelism dedicated to limited resources. As a case study, four typical CNNs are implemented on Stratix III EP3SL110, taking up on-chip memory. Compared with some existing works using the automated design flow, the implementations obtained by the proposed approach have achieved up to 17.13× GOPS. To the best estimate, our design has also achieved 1.33× resource efficiency and 3.61× power efficiency.

关键词： convolutional neural network parameterize parallelism

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Automatic Optimising CNN with Depthwise Separable Convolution on fpga: (Abstact Only) 18

Automatic Optimising CNN with Depthwise Separable Convolutio...

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Proceedings of the 2018 acm/sigda international symposium on field-programmable gate arrays

作者： Ruizhe Zhao Xinyu Niu Wayne Luk Imperial College London London United Kingdom

ISBN: (纸本)9781450356145

Convolution layers in Convolutional Neural Networks (CNNs) are effective in vision feature extraction but quite inefficient in computational resource usage. Depthwise separable convolution layer has been proposed in recent publications to enhance the efficiency without reducing the effectiveness by separately computing the spatial and cross-channel correlations from input images and has proven successful in state-of-the-art networks such as MobileNets [1] and Xception [2]. Based on the facts that depthwise separable convolution is highly structured and uses limited resources, we argue that it can well fit reconfigurable platforms like fpga. To benefit fpga platforms with this new layer, in this paper, we present a novel framework that can automatically generate and optimise hardware designs for depthwise separable CNNs. Besides, in our framework, existing conventional CNNs can be systematically converted to ones whose standard convolution layers are selectively replaced with functionally identical depthwise separable convolution layers, by carefully balancing the trade-off among speed, accuracy, and resource usage through resource usage modelling and network fine-tuning. Results show that hardware designs generated by our framework can reach at most 231.7 frames per second regarding MobileNets, and for VGG-16 [3], we gain 3.43 times speed-up and 3.54% accuracy decrease on the ImageNet [4] dataset comparing the original model and a layer replaced one.

关键词： depthwise separable convolution. design space exploration convolutional neural network

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Understanding Performance Differences of fpgas and GPUs: (Abtract Only) 18

Understanding Performance Differences of FPGAs and GPUs: (Ab...

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Proceedings of the 2018 acm/sigda international symposium on field-programmable gate arrays

作者： Jason Cong Zhenman Fang Michael Lo Hanrui Wang Jingxian Xu Shaochong Zhang University of California Los Angeles Los Angeles CA USA University of California Los Angeles and Xilinx Los Angeles CA USA University of California Los Angeles and Fudan University Los Angeles CA USA

ISBN: (纸本)9781450356145

The notorious power wall has significantly limited the scaling for general-purpose processors. To address this issue, various accelerators, such as GPUs and fpgas, emerged to achieve better performance and energy-efficiency. Between these two programmable accelerators, a natural question arises: which applications are better suited for fpgas, which for GPUs, and why?In this paper, our goal is to better understand the performance differences between fpgas and GPUs and provide more insights to the community. We intentionally start with a widely used GPU-friendly benchmark suite Rodinia, and port 11 of the benchmarks (15 kernels) onto fpgas using the more portable and programmable high-level synthesis C. We provide a simple five-step strategy for fpga accelerator designs that can be easily understood and mastered by software programmers, and present a quantitative performance breakdown of each step. Then we propose a set of performance metrics, including normalized operations per cycle (OPC_norm) for each pipeline, and effective parallel factor (effective_para_factor), to compare the performance of GPU and fpga accelerator designs. We find that for 6 out of the 15 kernels, today's fpgas can provide comparable performance or even achieve better performance, while only consume about 1/10 of GPUs' power (both on the same technology node). We observe that fpgas usually have higher OPC_norm in most kernels in light of their customized deep pipeline but lower effective_para_factor due to far lower memory bandwidth than GPUs. Future fpgas should increase their off-chip bandwidth and clock frequency to catch up with GPUs.

关键词： fpga gpu rodinia accelerator

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