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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是421-430 订阅

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Prototyping dynamic task migration on heterogeneous reconfigurable systems 28

Prototyping dynamic task migration on heterogeneous reconfig...

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2017 28th international symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, RSP 2017

作者： Wicaksana, Arief Bourge, Alban Muller, Olivier Sasongko, Arif Rousseau, Frédéric Univ. Grenoble Alpes TIMA CNRS Grenoble France Institut Teknologi Bandung Bandung Indonesia

ISBN: (纸本)9781450354189

Reconfigurable devices, such as fpgas, have been known to offer an excellent performance and a high efficiency in computation. Due to their improving capacity and more efficient architecture recently, there are growing interests in using fpgas as coprocessors in reconfigurable systems. However, fpgas still lack the support in dynamic scheduling, e.g. to manage multiple tasks or users in a system. Performing runtime task relocation or load distribution is not possible unless the reconfigurable system supports dynamic task migration. Such ability requires the automation of configuration and context management in reconfigurable architecture, which is not available in the existing solutions. In this paper, we propose a framework for prototyping dynamic task migration between heterogeneous fpgas. A task running on one fpga can be suspended and resumed on another fpga with different architecture. The extraction and restoration of fpga registers and memory values are possible due to the task-specific extraction mechanism provided by the tasks. The proposed framework exploits a high-performance embedded processor tightly-coupled to an fpga to automatically manage the configuration and context. It utilizes two popular heterogeneous reconfigurable systems in the implementation, Xilinx Zynq ZC706 and Altera Arria V SoC. Tests are performed using graphical and non-graphical benchmark applications and performance results are presented. © 2017 acm.

关键词： field programmable gate arrays (fpga)

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Towards Efficient Design Space Exploration of fpga-based Accelerators for Streaming HPC Applications 17

Towards Efficient Design Space Exploration of FPGA-based Acc...

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acm/sigda international symposium on field-programmable gate arrays

作者： Koraei, Mostafa Jahre, Magnus Fatemi, S. Omid Univ Tehran Tehran Iran NTNU Trondheim Trondheim Norway

ISBN: (纸本)9781450343541

Streaming HPC applications are data intensive and have widespread use in various fields (e.g., Computational Fluid Dynamics and Bioinformatics). These applications consist of different processing kernels where each kernel performs a specific computation on its input data. The objective of the optimization process is to maximize performance. fpgas show great promise for accelerating streaming applications because of their low power consumption combined with high theoretical compute capabilities. However, mapping an HPC application to a reconfigurable fabric is a challenging task. The challenge is exacerbated by need to temporally partition computational kernels when application requirements exceed resource availability. In this poster, we present work towards a novel design methodology for exploring design space of streaming HPC applications on fpgas. We assume that the designer can represent the target application with a Synchronous Data Flow Graph (SDFG). In the SDFG, the nodes are compute kernels and the edges signify data flow between kernels. The designer should also determine the problem size of the application and the volume of raw data on each memory source of the SDFG. The output of our method is a set of fpga configurations that each contain one or more SDFG nodes. The methodology consists of three main steps. In Step 1, we enumerate the valid partitions and the base configurations. In Step 2, we find the feasible base configurations given the hardware resources available and a library of processing kernel implementations. Finally, we use a performance model to calculate the execution time of each partition in Step 3. Our current assumption is that it is advantageous to represent SDFG at a coarse granularity since this enables exhaustive exploration of the design space for practical applications. This approach has yielded promising preliminary results. In one case, the temporal configuration selected by our methodology outperformed the direct mapping by 3X.

关键词： Reconfigurable Computing fpga HPC SDFG Acceleration Application mapping

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Performance Comparison of Multiples and Target Detection with Imager-driven Processing Mode for Ultrafast-Imager: (Abstract Only) 18

Performance Comparison of Multiples and Target Detection wit...

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Proceedings of the 2018 acm/sigda international symposium on field-programmable gate arrays

作者： Xiaoyu Yu Dong Ye Tencent Shenzhen China Harbin Institute of Technology Harbin China

ISBN: (纸本)9781450356145

Latest vision tasks trend to be the real-time processing with high throughput frame rate and low latency. High spatiotemporal resolution imagers continue to spring up but only a few of them can be used in real applications owing to the excessive computational burden and lacking of suitable architecture. This paper presents a solution for target detection task in imager-driven processing mode (IMP), which takes shorter time in processing than the time gap between frames, even if the ulreafast imager run at full frame rate. High throughput pixel stream outputted from imager is analyzed base on multi features in a fully pipelined and bufferless architecture in fpga. A pyramid shape model consisting of 2-D Processing Element (PE) array is proposed to search the connected regions of target candidates distributed at different time slices, and extract corresponding features when the stream pass through. A Label based 1-D PE Array collects the feature flow generated by the pyramid according to their labels, and output the feature vector of each target candidate in real time. The proposed model has been tested in simulation and experiments for target detection with 0.8Gpixel/sec (2320×1726 with 192FPS) data stream input, and the latency is less than 1 microsecond.

关键词： fpga feature extraction target detection connected components labeling high speed camera high throughput data stream

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LEOSoC: An Open-Source Cross-Platform Embedded Linux Library for Managing Hardware Accelerators in Heterogeneous System-on-Chips(Abstract Only) 18

LEOSoC: An Open-Source Cross-Platform Embedded Linux Library...

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Proceedings of the 2018 acm/sigda international symposium on field-programmable gate arrays

作者： Andrea Guerrieri Sahand Kashani-Akhavan Mikhail Asiatici Pasquale Lombardi Bilel Belhadj Paolo Ienne École Polytechnique Fédérale de Lausanne Lausanne Switzerland Syderal SA Gals Switzerland

ISBN: (纸本)9781450356145

Modern heterogeneous SoCs (System-on-Chip) contain a set of Hard IPs (HIPs) surrounded by an fpga fabric for hosting custom Hardware Accelerators (HAs). However, efficiently managing such HAs in an embedded Linux environment involves creating and building custom device drivers specific to the target platform, which negatively impacts development cost, portability and time-to-market. To address this issue, we present LEOSoC, an open-source cross-platform embedded Linux library. LEOSoC reduces the development effort required to interface HAs with applications and makes SoCs easy to use for an embedded software developer who is familiar with the semantics of standard POSIX threads. Using LEOSoC does not require any specific version of the Linux kernel, nor to rebuild a custom driver for each new kernel release. LEOSoC consists of a base hardware system and a software layer. Both hardware and software are portable across SoC from various vendors and the library recognizes and auto-adapts to the target SoC platform on which it is running. Furthermore, LEOSoC allows the application to partially or completely change the structure of the HAs at runtime without rebooting the system by leveraging the underlying platforms? support for dynamic full/partial fpga reconfigurability. The system has been tested on multiple COTS (Commercial Off The Shelf) boards from different vendors, each one running different versions of Linux and, therefore, proving the real portability and usability of LEOSoC in a specific industrial design.

关键词： fpga soc reconfigurable computing heterogeneous computing partial reconfiguration

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Storage-Efficient Batching for Minimizing Bandwidth of Fully-Connected Neural Network Layers 17

Storage-Efficient Batching for Minimizing Bandwidth of Fully...

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acm/sigda international symposium on field-programmable gate arrays

作者： Shen, Yongming Ferdman, Michael Milder, Peter SUNY Stony Brook Stony Brook NY 11794 USA

ISBN: (纸本)9781450343541

Convolutional neural networks (CNNs) are used to solve many challenging machine learning problems. These networks typically use convolutional layers for feature extraction and fully-connected layers to perform classification using those features. Significant interest in improving the performance of CNNs has led to the design of CNN accelerators to improve their evaluation throughput and efficiency. However, work on CNN accelerators has mostly concentrated on accelerating the computationally-intensive convolutional layers, while a major bottleneck of the existing designs arises due to the data-intensive fully-connected layers. Unfortunately, the leading approaches to reducing bandwidth of the fully-connected layers are limited by the storage capacity of the on-chip buffers. We observe that, in addition to the possibility of reducing CNN weight transfer bandwidth by adding more on-chip buffers, it is also possible to reduce the size of the on-chip buffers at the cost of CNN input transfer. Paradoxically, shrinking the size of the on-chip buffers costs significantly less input bandwidth than the weight bandwidth saved by adding more buffers. Leveraging these observations, we develop a design methodology for fully-connected layer accelerators that require substantially less off-chip bandwidth by balancing between the input and weight transfers. Using 160KB of BRAM enables the prior work to reduce off-chip bandwidth by 5x on the most bandwidth-intensive fully-connected layers of the popular AlexNet and VGGNet-E networks. With our newly proposed methodology, using the same 160KB of BRAM produces a design with 71x bandwidth reduction on the same networks.

关键词： fpga accelerators Convolutional neural networks Bandwidth optimization

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Exploring Sparsity of Firing Activities and Clock Gating for Energy-Efficient Recurrent Spiking Neural Processors 22

Exploring Sparsity of Firing Activities and Clock Gating for...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Liu, Yu Jin, Yingyezhe Li, Peng Texas A&M Univ Dept Elect & Comp Engn College Stn TX 77843 USA

ISBN: (纸本)9781509060238

As a model of recurrent spiking neural networks, the Liquid State Machine (LSM) offers a powerful brain-inspired computing platform for pattern recognition and machine learning applications. While operated by processing neural spiking activities, the LSM naturally lends itself to an efficient hardware implementation via exploration of typical sparse firing patterns emerged from the recurrent neural network and smart processing of computational tasks that are orchestrated by different firing events at runtime. We explore these opportunities by presenting a LSM processor architecture with integrated on-chip learning and its fpga implementation. Our LSM processor leverage the sparsity of firing activities to allow for efficient event-driven processing and activity-dependent clock gating. Using the spoken English letters adopted from the TI46 [1] speech recognition corpus as a benchmark, we show that the proposed fpga-based neural processor system is up to 2 9 % more energy efficient than a baseline LSM processor with little extra hardware overhead.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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A Low-Power Deconvolutional Accelerator for Convolutional Neural Network Based Segmentation on fpga: Abstract Only 18

A Low-Power Deconvolutional Accelerator for Convolutional Ne...

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Proceedings of the 2018 acm/sigda international symposium on field-programmable gate arrays

作者： Shuanglong Liu Xinyu Niu Wayne Luk Imperial College London London United Kingdom Corerain Technologies Ltd. Shenzhen China

ISBN: (纸本)9781450356145

Convolutional Neural Networks (CNNs) based algorithms have been successful in solving image recognition problems, showing very large accuracy improvement. In recent years, deconvolution layers are widely used as key components in the state-of-the-art CNNs for end-to-end training and models to support tasks such as image segmentation. However, the deconvolution algorithms are computationally intensive which limits their applicability to real time applications. Particularly, there has been little research on the efficient implementations of deconvolution algorithms on fpga platforms. In this work, we propose and develop fully customized deconvolution architecture for CNN-based segmentation algorithms. Besides, memory sharing between the computation modules is proposed for the fpga-based CNN accelerator as well as for other optimization techniques. Furthermore, a hardware mapping framework is developed to automatically generate the high-throughput hardware design for any given CNN model on the target device. Finally, we implement our designs on Xilinx Zynq-7030 and the deconvolution accelerator achieves a performance of 25.6 GOPS under 200MHz working frequency and a performance density of 0.064 GOPS/DSP using 32-bit quantization, which significantly outperforms previous designs on fpgas. A real-time application of scene segmentation on Cityscapes Dataset is used to evaluate our CNN accelerator on Zynq-7030 board, and the system achieves a performance of 57.2 GOPS and 0.143 GOPS/DSP using 16-bit quantization, and supports up to 2 frames per second for 512x512 image inputs with a power consumption of only 3.2W.

关键词： convolutional neural networks (cnns) hardware acceleration deconvolution segmentation fpga

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Automatic Generation of Hardware Sandboxes for Trojan Mitigation in Systems on Chip 17

Automatic Generation of Hardware Sandboxes for Trojan Mitiga...

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acm/sigda international symposium on field-programmable gate arrays

作者： Bobda, Christophe Whitaker, Taylor Kamhoua, Charles Kwiat, Kevin Njilla, Laurent Univ Arkansas Fayetteville AR 72701 USA US Air Force Res Lab Washington DC 20330 USA

ISBN: (纸本)9781450343541

Component based design is one of the preferred methods to tackle system complexity, and reduce costs and time-to-market. Major parts of the system design and IC production are outsourced to facilities distributed across the globe, thus opening the door for malicious Trojan insertion. Hardware Sandboxing was introduce as a means to overcome the shortcomings of traditional static Trojan mitigation methods, which use intense simulation, verification, and physical tests to detect the evidence of malicious components before system deployment. The number of test patterns needed to activate with certainty potential hidden Trojans is very large for complex IPs and SoCs with dozens of inputs, outputs, states, and memory blocks, thus limiting the effectiveness of static testing methods. The rationale is to spend less effort testing pre-deployment. Instead, guards should be built around non-trusted components to catch malicious activities and prevent potential damage. While feasibility of hardware sandboxes has been proven with case studies and real-world applications, manual design was used and no systematic method was devised to automate the design process of system-on-chips that incorporate hardware sandboxes to provide high-level of security in embedded systems. In this work, we propose a method for automatic generation of hardware sandboxes in system-on-chips. Using the interface formalism of De Alfaro and Hetzinger to capture the interactions among components, along with the properties specification language to define non-authorized actions, sandboxes are generated and made ready for inclusion in a system-on-chip design. We leverage the concepts of composition, compatibility, and refinement to optimize resources across the boundary of single component and provide minimal resource consumption. With results on benchmarks implemented in fpga, we prove that our approach can provide high-level of security, with less resource and no increase in delay.

关键词： Hardware Sandboxes Hardware Trojan SoC Security fpga Automatic Generation

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fpga-based LSTM Acceleration for Real-Time EEG Signal Processing: (Abstract Only) 18

FPGA-based LSTM Acceleration for Real-Time EEG Signal Proces...

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Proceedings of the 2018 acm/sigda international symposium on field-programmable gate arrays

作者： Zhe Chen Andrew Howe Hugh T. Blair Jason Cong University of California Los Angeles Los Angeles CA USA

ISBN: (纸本)9781450356145

Closed-loop neurofeedback is a growing area of research and development for novel therapies to treat brain disorders. A neurofeedback device can detect disease symptoms (such as motor tremors or seizures) in real time from electroencephalogram (EEG) signals, and respond by rapidly delivering neurofeedback stimulation that relieves these symptoms. Conventional EEG processing algorithms rely on acausal filters, which impose delays that can exceed the short feedback latency required for closed-loop stimulation. In this paper, we first introduce a method for causal filtering using long short-term memory (LSTM) networks, which radically reduces the filtering latency. We then propose a reconfigurable architecture that supports time-division multiplexing of LSTM inference engines on a prototype neurofeedback device. We implemented a 128-channel EEG signal processing design on a Zynq-7030 device, and demonstrated its feasibility. Then, we further scaled up the design onto Zynq-7045 and Virtex-690t devices to achieve high performance and energy efficient implementations for massively parallel brain signal processing. We evaluated the performance against optimized implementations on CPU and GPU at the same CMOS technology node. Experiment results show that the Virtex-690t can achieve 1.32x and 11x speed-up against the K40c GPU and the multi-thread Xeon E5-2860 CPU, respectively, while fpga achieves 6.1x and 26.6x energy efficiency compared to the GPU and CPU.

关键词： reconfigurable logic neurofeedback electroencephalography multiplexing phase detection

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Simulation-based circuit-activity estimation for fpgas containing hard blocks 28

Simulation-based circuit-activity estimation for FPGAs conta...

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2017 28th international symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, RSP 2017

作者： Seeley, Sean Sankaranaryanan, Vidya Deveau, Zack Patros, Panagiotis Kent, Kenneth B. Faculty of Computer Science University of New Brunswick Canada

ISBN: (纸本)9781450354189

fpgas are electronic devices that are programmable and can functionally perform equivalently to a number of other circuits. fpgas are used for both rapid and cheap prototyping of new circuit designs as well as for replacing outdated chip models. Due to their complexity, circuits cannot be practically designed by hand;instead, specialized Computer Aided Design (CAD) software performs this complex task. A major concern for devices is power requirements, which can have adverse effects on both the environment and users. The power requirements of a circuit can be directly connected with its activity, which can be estimated by the CAD tools. In this work, we focus on the open source Verilog-To-Routing (VTR) CAD software and propose an improved activity estimation tool using VTR's synthesizer (Odin II) that extends beyond the capabilities of its current estimator (ACE2), such as proper black box activity propagation and support for circuits containing no clocks or more than one clock. Our results are experimentally evaluated with VTR's fpga architectures and benchmark circuits. © 2017 acm.

关键词： field programmable gate arrays (fpga)

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