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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是491-500 订阅

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Mapping-aware constrained scheduling for LUT-based fpgas 15

Mapping-aware constrained scheduling for LUT-based FPGAs

引用

acm/sigda international symposium on field-programmable gate arrays, fpga 2015

作者： Tan, Mingxing Dai, Steve Gupta, Udit Zhang, Zhiru School of Electrical and Computer Engineering Cornell University IthacaNY United States

ISBN: (纸本)9781450333153

Scheduling plays a central role in high-level synthesis, as it inserts clock boundaries into the untimed behavioral model and greatly impacts the performance, power, and area of the synthesized circuits. While current scheduling techniques can make use of pre-characterized delay values of individual operations, it is difficult to obtain accurate timing estimation on a cluster of operations without considering technology mapping. This limitation is particularly pronounced for fpgas where a large logic network can be mapped to only a few levels of look-up tables (LUT). In this paper, we propose MAPS, a mapping-aware constrained scheduling algorithm for LUT-based fpgas. Instead of simply summing up the estimated delay values of individual operations, MAPS jointly performs technology mapping and scheduling, creating the opportunity for more aggressive operation chaining to minimize latency and reduce area. We show that MAPS can produce a latency-optimal solution, while supporting a variety of design timing requirements expressed in a system of difference constraints. We also present an efficient incremental scheduling technique for MAPS to effectively handle resource constraints. Experimental results with real-life benchmarks demonstrate that our proposed algorithm achieves very promising improvements in performance and resource usage when compared to a state-of-the-art commercial high-level synthesis tool targeting Xilinx fpgas. © Copyright acm.

关键词： field programmable gate arrays (fpga)

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A High-throughput Architecture for Lossless Decompression on fpga Designed Using HLS (Abstract Only) 16

A High-throughput Architecture for Lossless Decompression on...

引用

Proceedings of the 2016 acm/sigda international symposium on field-programmable gate arrays

作者： Jie Lei Yuting Chen Yunsong Li Jason Cong Xidian University & UCLA Xi'an China UCLA Los Angeles CA USA Xidian University Xi'an China

ISBN: (纸本)9781450338561

In the field of big data applications, lossless data compression and decompression can play an important role in improving the data center's efficiency in storage and distribution of data. To avoid becoming a performance bottleneck, they must be accelerated to have a capability of high speed data processing. As fpgas begin to be deployed as compute accelerators in the data centers for its advantages of massive parallel customized processing capability, power efficiency and hardware reconfiguration. It is promising and interesting to use fpgas for acceleration of data compression and decompression. The conventional development of fpga accelerators using hardware description language costs much more design efforts than that of CPUs or GPUs. High level synthesis (HLS) can be used to greatly improve the design productivity. In this paper, we present a solution for accelerating lossless data decompression on fpga by using HLS. With a pipelined data-flow structure, the proposed decompression accelerator can perform static Huffman decoding and LZ77 decompression at a very high throughput rate. According to the experimental results conducted on fpga with the Calgary Corpus data benchmark, the average data throughput of the proposed decompression core achieves to 4.6 Gbps while running at 200 MHz.

关键词： lossless decompression hls fpga accelerator

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200 MS/s ADC implemented in a fpga employing TDCs 15

200 MS/s ADC implemented in a FPGA employing TDCs

引用

acm/sigda international symposium on field-programmable gate arrays, fpga 2015

作者： Homulle, Harald Regazzoni, Francesco Charbon, Edoardo Delft University of Technology Delft Netherlands USI ALaRI Lugano Switzerland

ISBN: (纸本)9781450333153

Analog signals are used in many applications and systems, such as cyber physical systems, sensor networks and automotive applications. These are also applications where the use of fpgas is continuously growing. To date, however there is no direct integration between fpgas, which are digital, and the analog world (except for the newest generation of fpgas). Currently, an external analog-to-digital converter (ADC) has to be added to the system, thus limiting its overall compactness and exibility. To address this issue we propose a novel architecture implementing a high speed ADC in reconfigurable devices. The system exploits picosecond resolution time-to-digital converters (TDCs) to reach a conversion as fast as its clock speed. The resulting analog-through-time-to-digital converter (ATDC) can achieve a sampling rate of 200 MS/s with a 7 bit resolution for signals ranging from 0 to 2.5 V. Except for the external resistor needed for the analog reference ramp, the system is fully integrated inside the target fpga. Moreover, our design can be easily scaled for multichannel ADCs, proving the suitability of reconfigurable devices for applications requiring a deep integration between analog and digital world. © Copyright acm.

关键词： Sensor networks

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An fpga-SOC Based Accelerating Solution for N-body Simulations in MOND (Abstract Only) 16

An FPGA-SOC Based Accelerating Solution for N-body Simulatio...

引用

Proceedings of the 2016 acm/sigda international symposium on field-programmable gate arrays

作者： Bo Peng Tianqi Wang Xi Jin Chuanjun Wang School of Physical Sciences USTC Hefei China Chinese Academy of Sciences Kunming China

ISBN: (纸本)9781450338561

Modified Newtonian dynamics (MOND) has shown a great success as a modified-potential theory of gravity. In this paper, we present a highly integrated accelerating solution for N-body MOND simulations. By using the fpga-SoC, which integrates both fpga and SOC (system on chip) in one chip, our solution exhibits potential for better performance, higher integration, and lower power consumption. To handle the calculation bottleneck of potential summation, on one hand, we develop a strategy to simplify the pipeline, in which the square calculation task is conducted by the DSP48E1 of Xilinx 7 series fpgas, so as to reduce the logic resource consumption of each pipeline; on the other hand, advantages of particle-mesh scheme are taken to overcome the bottleneck on bandwidth. Our experiment results show that 2 more pipelines can be integrated in Zynq-7020 fpga-SoC with the simplified pipeline, and the bandwidth requirement is reduced significantly. Furthermore, our accelerating solution has a full range of advantages over different processors. Compared with GPU, our work is about better in both performance per Watt and performance per cost.

关键词： fpga-soc n-body mond accelerating

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Delay-bounded routing for shadow registers 15

Delay-bounded routing for shadow registers

引用

acm/sigda international symposium on field-programmable gate arrays, fpga 2015

作者： Hung, Eddie Levine, Joshua M. Stott, Edward Constantinides, George A. Luk, Wayne Department of Electrical and Electronic Engineering Imperial College London United Kingdom Department of Computing Imperial College London United Kingdom

ISBN: (纸本)9781450333153

The on-chip timing behaviour of synchronous circuits can be quantified at run-time by adding shadow registers, which allow designers to sample the most critical paths of a circuit at a different point in time than the user register would normally. In order to sample these paths precisely, the path skew between the user and the shadow register must be tightly controlled and consistent across all paths that are shadowed. Unlike a custom IC, fpgas contain prefabricated resources from which composing an arbitrary routing delay is not trivial. This paper presents a method for inserting shadow registers with a minimum skew bound, whilst also reducing the maximum skew. To preserve circuit timing, we apply this to fpga circuits post place-and-route, using only the spare resources left behind. We find that our techniques can achieve an average STA reported delay bound of ±200ps on a Xilinx device despite incomplete timing information, and achieve

关键词： field programmable gate arrays (fpga)

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fpga Power Estimation Using Automatic Feature Selection (Abstract Only) 16

FPGA Power Estimation Using Automatic Feature Selection (Abs...

引用

Proceedings of the 2016 acm/sigda international symposium on field-programmable gate arrays

作者： Yunxuan Yu Lei He University of California Los Angeles LA CA USA

ISBN: (纸本)9781450338561

Because layout stage consumes the lion share of fpga synthesis runtime, pre-layout power estimation can be viewed as an early stage estimation and is needed for power minimization at the early design stage. Consisting two phases of feature selection and model training, data mining is effective for data based modeling, yet it has not been applied in a rigid fashion for fpga power estimation as the existing algorithms can be viewed as model training using features selected manually. In this paper, we apply machine learning with automatic feature selection to pre- and post- logic synthesis estimations, named pre-synthesis and post-synthesis estimation. Experiments using Lattice Diamond MachXO2 family show that compared to the post-layout power simulation, post-synthesis estimation is 20x faster with 8.62% average error, while pre-synthesis estimation is 600x faster with considerably larger error that still needs further improvement. Furthermore, compared to existing algorithms using manually selected features, our post-synthesis estimation using automatic feature selection reduces error by 2-3 times. Finally, the ranking of features is able to provide insights for power minimization.

关键词： rtl power estimation svm fpga feature selection

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Low-Swing Signaling for fpga Power Reduction (Abstract Only) 16

Low-Swing Signaling for FPGA Power Reduction (Abstract Only)

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Proceedings of the 2016 acm/sigda international symposium on field-programmable gate arrays

作者： Sayeh Sharifymoghaddam Ali Sheikholeslami University of Toronto Toronto ON Canada

ISBN: (纸本)9781450338561

fpgas are widely used in digital circuits implementation because of their lower non-recurring engineering cost and shorter time-to-market in comparison with ASICs. However, there are still area, performance, and energy efficiency gaps between fpgas and ASICs. In this work, we propose a new fpga architecture to narrow the energy efficiency gap. Since more than 62% of fpga power is consumed in its interconnect, we target power consumption of the interconnect and try to reduce dynamic power consumption of this part using low-swing signaling technique. To implement low-swing signaling, high-to-low and low-to-high voltage level converters are added to the switch boxes and connection blocks of the basic architecture. Simulation results on 20 largest MCNC circuits and 19 computational benchmarks confirm that the proposed architecture achieves an average of 13.5% total power reduction with the cost of less than 1% area and delay overhead. To the authors? knowledge, the proposed architecture in this work is the first architecture that provides low-swing signaling for single driver unidirectional routing scheme. Moreover, the proposed architecture has the maximum CAD tool flexibility and no extra constraint is required for the placement and routing algorithms.

关键词： fpga 1. low-swing global interconnect

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Energy and memory efficient mapping of bitonic sorting on fpga 15

Energy and memory efficient mapping of bitonic sorting on FP...

引用

acm/sigda international symposium on field-programmable gate arrays, fpga 2015

作者： Chen, Ren Siriyal, Sruja Prasanna, Viktor Ming Hsieh Department of Electrical Engineering University of Southern California Los Angeles90089 United States

ISBN: (纸本)9781450333153

Parallel sorting networks are widely employed in hardware implementations for sorting due to their high data paral- lelism and low control overhead. In this paper, we propose an energy and memory efficient mapping methodology for implementing bitonic sorting network on fpga. Using this methodology, the proposed sorting architecture can be built for a given data parallelism while supporting continuous data streams. We propose a streaming permutation network (SPN) by "folding" the classic Clos network. We prove that the SPN is programmable to realize all the interconnection patterns in the bitonic sorting network. A low cost design for sorting with minimal resource usage is obtained by reusing one SPN. We also demonstrate a high throughput design by trading off area for performance. With a data parallelism of p (2≤ p≤ N= log2 N), the high throughput design sorts an N-key sequence with latency O(N=p), throughput (# of keys sorted per cycle) O(p) and uses O(N) memory. This achieves optimal memory efficiency (defined as the ratio of throughput to the amount of on-chip memory used by the design) of O(p=N). Another noteworthy feature of the high throughput design is that only single-port memory rather than dual-port memory is required for processing continu- ous data streams. This results in 50% reduction in memory consumption. Post place-and-route results show that our architecture demonstrates 1.3x∼1.6x improvment in energy efficiency and 1.5x∼5.3x better memory efficiency compared with the state-of-the-art designs. © Copyright acm.

关键词： field programmable gate arrays (fpga)

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A 1 GSa/s, Reconfigurable Soft-core fpga ADC (Abstract Only) 16

A 1 GSa/s, Reconfigurable Soft-core FPGA ADC (Abstract Only)

引用

Proceedings of the 2016 acm/sigda international symposium on field-programmable gate arrays

作者： Stefan Visser Harald Homulle Edoardo Charbon TU Delft Delft Netherlands

ISBN: (纸本)9781450338561

There exist many applications where analog interfacing is abundant, e.g. sensor networks, automotive, industrial control, (quantum) physics etc. In those fields the use of fpgas is continuously growing, however a direct link between the analog world and the digital fpga is still missing (except for the newest generation of fpgas, where analog-to-digital conversion is present, but limited in performance). External analog-to-digital converters (ADCs) are combined together with the fpga to form a complete, application-specific system. This system is thus limited in compactness, flexibility, and *** address those issues we propose an ADC architecture, implemented in a fpga, that is fully reconfigurable and easy to calibrate. This allows to alter the design, according to the system requirements. Therefore it can be used in a wide range of operating conditions and adjusted to changes in supply voltage and fpga *** architecture employs time-to-digital converters (TDCs) and phase interpolation techniques to reach a sampling rate higher than the clock frequency (400 MHz) of up to 1.2 GSa/s. The resulting fpga ADC can achieve a 6 bit resolution over a 0.6 to 1.9 V input range. The system non-linearities (INL, DNL) are less than 0.45 LSB. The main advantages of this architecture are its scalability and reconfigurability, enabling applications with changing demands, on one single platform.

关键词： fpga reconfigurable soft-core tdc time-to-digital converter adc analog-to-digital converter calibration

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Machine-Learning driven Auto-Tuning of High-Level Synthesis for fpgas (Abstract Only) 16

Machine-Learning driven Auto-Tuning of High-Level Synthesis ...

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Proceedings of the 2016 acm/sigda international symposium on field-programmable gate arrays

作者： Li Ting Harri Wijaya Nachiket Kapre Nanyang Technological University Singapore Singapore

ISBN: (纸本)9781450338561

Modern High-Level Synthesis (HLS) tools allow C descriptions of computation to be compiled to optimized low-level RTL, but expose a range of manual optimization options, compiler directives and tweaks to the developer. In many instances, this results in a tedious iterative development flow to meet resource, timing and power constraints which defeats the purpose of adopting the high-level abstraction in the first place. In this paper, we show how to use Machine Learning routines to predict the impact of HLS compiler optimization on final fpga utilization metrics. We compile multiple variations of the high-level C code across a range of compiler optimizations and pragmas to generate a large design space of candidate solutions. On the Machsuite benchmarks, we are able to train a linear regression model to predict resources, latency and frequency metrics with high accuracy (R2 > 0.75). We expect such developer-assistance tools to (1) offer insight to drive manual selection of suitable directive combinations, and (2) automate the process of selecting directives in the complex design space of modern HLS design.

关键词： machine learning timing closure fpga cad

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