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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是511-520 订阅

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A Full-Capacity Local RoutingArchitecture for fpgas (Abstract Only) 16

A Full-Capacity Local RoutingArchitecture for FPGAs (Abstrac...

引用

Proceedings of the 2016 acm/sigda international symposium on field-programmable gate arrays

作者： Xifan Tang Pierre-Emmanuel Gaillardon Giovanni De Micheli EPFL Lausanne Switzerland

ISBN: (纸本)9781450338561

Reconfigurable systems employ highly-routable local routing architecture to interconnect generic fine-grain logic blocks. Commercial fpgas employ 50% sparse crossbars rather than fully-connected crossbars in their local routing architecture to trade off between the area and routability of the Logic Blocks (LBs). While the input crossbar provides good routability and logic equivalence for the inputs of the LB, the outputs of the LBs are typically assigned to a physical location. This lack of flexibility brings strong constraints to the global net router. Here, we propose a novel local routing architecture that guarantees full logic equivalence on all input and output pins of the LBs. First, we introduce full-capacity crossbars to interconnect the outputs of the fine-grain Logic Elements (LEs) to the output pins of the LBs. Second, in the local routing, we use a combination of fully-connected and full-capacity crossbars. The full-capacity crossbars are used for the feedback connections in place of the standard fully-connected crossbars to ensure a full routability while reducing the area footprint. Fully-connected crossbars are still employed for the input connections to maintain the logic equivalence of the inputs. As a result, the novel local routing architecture enhances the routability of the LB clusters without any area overhead. By granting the outputs with logic equivalence, the proposed local routing architecture unlocks the full optimization potential of fpga routers. Architectural simulations show that without any modification on Verilog-to-Routing (VTR) tool suites, when a commercial fpga architecture is considered and over a wide set of benchmarks, the novel local routing architecture can reduce 10% channel width and 11% routing area with 10% less area×delay×power on average. Therefore, the novel local routing architecture enhances the routability of fpga, and brings opportunities in realizing larger implementations on a single fpga chip.

关键词： local routing crossbars full-capacity fpga

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Implentation of onboard JPEG XR compression on a low clock frequency fpga

Implentation of onboard JPEG XR compression on a low clock f...

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IEEE international symposium on Geoscience and Remote Sensing (IGARSS)

作者： Hao Chen Xinyu Guo Ye Zhang Department of Information Engineering Harbin Institute of Technology

ISBN: (纸本)9781509033331

When dealing with the enormous remote sensing image, JPEG XR offers similar compression rate compared with JPEG2000, while consumes nearly the same resource as JPEG. Taking the limitation of power and computational resources onboard into consideration, fpga-based hardware solution stands out with advantages of less resource requirement and higher speed. And the operation of JPEG XR is all in integer, so the image compression algorithm is feasible to implement. To realize high-throughput pipeline architecture for onboard image compression with low clock frequency, fpga is adopted to perform the parallel architecture for JPEG XR lossy compression. The parallel architecture is summed up into five modules: pre-filter module, photo core transform (PCT) module, quantification module, predictive coding module and entropy coding module. Experimental results demonstrate the coding speed is 0.437 pixel per clock, speed of code stream is 41.7Mbyte/s at 100MHz clock frequency.

关键词： Transform coding Pipelines Quantization (signal) Image coding field programmable gate arrays Entropy coding

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ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architecture (Abstact Only) 16

ARAPrototyper: Enabling Rapid Prototyping and Evaluation for...

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Proceedings of the 2016 acm/sigda international symposium on field-programmable gate arrays

作者： Yu-Ting Chen Jason Cong Zhenman Fang Peipei Zhou University of California Los Angeles Los Angeles CA USA

ISBN: (纸本)9781450338561

Compared to conventional general-purpose processors, accelerator-rich architectures (ARAs) can provide orders-of-magnitude performance and energy gains. In this paper we design and implement the ARAPrototyper to enable rapid design space explorations for ARAs in real silicons and reduce the tedious prototyping efforts. First, ARAPrototyper provides a reusable baseline prototype with a highly customizable memory system, including interconnect between accelerators and buffers, interconnect between buffers and last-level cache (LLC) or DRAM, coherency choice at LLC or DRAM, and address translation support. To provide more insights into performance analysis, ARAPrototyper adds several performance counters on the accelerator side and leverages existing performance counters on the CPU side. Second, ARAPrototyper provides a clean interface to quickly integrate a user?s own accelerators written in high-level synthesis (HLS) code. Then, an ARA prototype can be automatically generated and mapped to a Xilinx Zynq SoC. To quickly develop applications that run seamlessly on the ARA prototype, ARAPrototyper provides a system software stack and abstracts the accelerators as software libraries for application developers. Our results demonstrate that ARAPrototyper enables a wide range of design space explorations for ARAs at manageable prototyping efforts and 4,000 to 10,000X faster evaluation time than full-system simulations. We believe that ARAPrototyper can be an attractive alternative for ARA design and evaluation.

关键词： customized memory system performance evaluation fpga prototyping accelerator-rich architecture accelerator integration

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fpga 2015 chairs' welcome

FPGA 2015 - 2015 ACM/SIGDA International Symposium on Field-...

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fpga 2015 - 2015 acm/sigda international symposium on field-programmable gate arrays 2015年

作者： Chen, Deming Constantinides, George

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The Digital Bidirectional Function as a Hardware Security Primitive: Architecture and Applications 20

The Digital Bidirectional Function as a Hardware Security Pr...

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IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Xu, Teng Potkonjak, Miodrag Univ Calif Los Angeles Dept Comp Sci Los Angeles CA 90024 USA

ISBN: (纸本)9781467380096

Security and low power have emerged to become two essential requirements to modern design. In this paper, we have proposed a new hardware security primitive: digital bidirectional function (DBF) designed on fpga to meet both criteria. The DBF has two forms of functions and implements two mappings of opposite directions. The DBF can be easily implemented using hierarchical lookup-table (LUT) structures with low delay and power overhead. In terms of applications, we demonstrate how DBF is applied in the protocol of secure message transfer and compare its power/bandwidth consumption with other cryptographic approaches. Our results indicate that the energy consumption of DBF outperforms the traditional ciphers by averagely two to three orders of magnitude.

关键词： DESIGN BASIS FIRES hardware security modern design energy consumption message passing field programmable gate arrays Primitive Bidirectional

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Enhanced TERO-PUF Implementations and Characterization on fpgas (Abstract Only) 16

Enhanced TERO-PUF Implementations and Characterization on FP...

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Proceedings of the 2016 acm/sigda international symposium on field-programmable gate arrays

作者： Cédric Marchand Lilian Bossuet Abdelkarim Cherkaoui Laboratoire Hubert Curien University of Lyon Saint-Etienne France TIMA Laboratory Grenoble France

ISBN: (纸本)9781450338561

Physical unclonable functions (PUF) are a promising approach in design for trust and security. A PUF derives a unique identifier using physical characteristics of different dies containing an identical circuit, so it can be used to authenticate chips and for identification. The transient effect ring oscillator (TERO) PUF is based on the extraction of entropy due to process variations by comparing TERO cells characteristics. The TERO cell is designed and implemented with a symmetric structure that requires special selection of the gates used and the delays of all connections inside the cell. Implementing this cell in fpgas is challenging because the structure of fpgas does not automatically allow designers to choose connections between elements. However, by manually specifying constraints and using specific features of the target fpga family, the symmetry of the TERO cell can be established and reproduced in larger designs. In this work, the design of the TERO cell is described for two different FGPA technologies (45nm Xilinx Spartan 6 and 28nm Altera Cyclone V). The statistical characterization of the TERO-PUF with the two targeted fpgas has resulted in a uniqueness of 48.46% with Spartan 6 and 47.62% with Cyclone V. The result for the steadiness is 2.63% with Spartan 6 and 1.8% with Cyclone V. These results are close to the results obtained by several works that use ring oscillator RO-PUF which are considered the best candidate for PUF implementation on fpgas. However, TERO-PUF is less sensitive to electromagnetic analysis than RO-PUF. Additionally, unlike RO-PUF, TERO-PUF is able to generate multiple bits per challenge (from one to three) and we have shown during the statistical characterization that the TERO-PUF provides from 0.85 to 1 bits of entropy per response *** a conclusion, our work clearly shows that TERO-PUF is an serious alternative to RO-PUF for PUF implementation on fpgas with strong statistical characteristics and more security than RO-PUF.

关键词： physical unclonable function puf design puf characterization fpga

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fpga'12 - Proceedings of the 2012 acm/sigda international symposium on field programmable gate arrays

FPGA'12 - Proceedings of the 2012 ACM/SIGDA International Sy...

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2012 acm/sigda international symposium on field programmable gate arrays, fpga'12

ISBN: (纸本)9781450311557

The proceedings contain 36 papers. The topics discussed include: speedy fpga-based packet classifiers with low on-chip memory requirements;a real-time stereo vision system using a tree-structured dynamic programming on fpga;incremental clustering applied to radar deinterleaving: a parameterized fpga implementation;communication visualization for bottleneck detection of high-level synthesis applications;a mixed precision Monte Carlo methodology for reconfigurable accelerator systems;saturating the transceiver bandwidth: switch fabric design on fpgas;saturating the transceiver bandwidth: switch fabric design on fpgas;limit study of energy & delay benefits of component-specific routing;impact of fpga architecture on resource sharing in high-level synthesis;and securing netlist-level fpga design through exploiting process variation and degradation.

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Single-Loop Approach to 2-D Wavelet Lifting with JPEG 2000 Compatibility 27

Single-Loop Approach to 2-D Wavelet Lifting with JPEG 2000 C...

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IEEE 27th international symposium on Computer Architecture and High Performance Computing

作者： Barina, David Musil, Petr Musil, Martin Zemcik, Pavel Brno Univ Technol CS-61090 Brno Czech Republic

ISBN: (纸本)9781467386210

A novel approach to 2-D single-loop wavelet lifting with compatibility to JPEG 2000 is presented in this paper. A newly developed 2-D core of CDF 5/3 wavelet filter is presented that, using a new sequence of operations, simplify the design. Moreover, the proposed approach, that uses one pass for 2-D transform, directly produces final output and reduces significantly the need for storing intermediate results into memory. All the proposed structures can be efficiently pipelined in hardware. This paper describes the proposed approach, its implementation in fpga, cost of such implementation, and brings an experimental evaluation as well as discussion of the features of the approach.

关键词： Discrete wavelet transforms field programmable gate arrays

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An Automated Design Framework for Floating Point Scientific Algorithms using field programmable gate arrays (fpgas) (Abstract Only) 15

An Automated Design Framework for Floating Point Scientific ...

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Proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Michaela E. Amoo Youngsoo Kim Vance Alford Shrikant Jadhav Naser I. El-Bathy Clay S. Gloster Jr. Howard University Washington DC USA North Carolina A&T State University Greensboro NC USA

ISBN: (纸本)9781450333153

This paper presents a reconfigurable computing environment while addressing the problem of porting High Performance Computing (HPC) applications directly to field programmable gate arrays (fpgas)-based architectures. The objectives of this research are developing a comprehensive floating point library of essential functions for scientific applications; demonstrate order of magnitude speedup of reconfigurable computing applications, demonstrating the effectiveness of automated design framework for both development and test of scientific algorithms. The developed framework can be reused in various scientific applications which shares kernel functions. The study of this research has identified an exponential function as a kernel for cellular ophthalmoscopy camera processing, traffic monitoring and light wave simulation. The paper demonstrates 30x speedup of these kernels in three algorithms using its novel architecture and its automated toolset. Exponential kernel generation case study and its flexible hardware implementation on an fpga has been validated onto a Xilinx LX-100 device and the Nallatech H101-PCIXM fpga board.

关键词： floating point exponential hpc fpga

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Acceleration of Synthetic Aperture Radar (SAR) Algorithms using field programmable gate arrays (fpgas) (Abstract Only) 15

Acceleration of Synthetic Aperture Radar (SAR) Algorithms us...

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Proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Youngsoo Kim William Harding Clay S. Gloster Winser Alexander North Carolina A&T State University Greensboro NC USA North Carolina State University Raleigh NC USA

ISBN: (纸本)9781450333153

Algorithms for radar signal processing, such as Synthetic Aperture Radar (SAR) are computationally intensive and require considerable execution time on a general purpose processor. Reconfigurable logic can be used to off-load the primary computational kernel onto a custom computing machine in order to reduce execution time by an order of magnitude as compared to kernel execution on a general purpose processor. Specifically, field programmable gate arrays (fpgas) can be used to house hardware-based custom implementations of these kernels to speed up these applications. In this paper, we demonstrate a methodology for algorithm acceleration. We used SAR as a case study to illustrate the tremendous potential for algorithm acceleration offered by fpgas. Initially, we profiled the SAR algorithm and implemented a homomorphic filter using a hardware implementation of the natural logarithm. Experimental results show an average speed-up of 188 when using the fpga-based hardware accelerator as opposed to using a software implementation running on a typical general purpose processor.

关键词： floating point fpga logarithmic synthetic aperture radar homomorphic

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