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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是531-540 订阅

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A soft error vulnerability analysis framework for xilinx fpgas 14

A soft error vulnerability analysis framework for xilinx FPG...

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2014 acm/sigda international symposium on field programmable gate arrays, fpga 2014

作者： Sari, Aitzan Agiakatsikas, Dimitris Psarakis, Mihalis Department of Informatics University of Piraeus Greece

ISBN: (纸本)9781450326711

Today's SRAM-based fpgas provide a reach set of computing resources which makes them attractive in demanding and critical application domains, such as avionics and space. Unfortunately, their high reliance on SRAM configuration memory arise reliability issues due to the single-event upsets (SEUs). Considering the criticality of these applications, the vulnerability analysis of fpga designs to SEUs becomes essential part of the design flow. In this context, we present an open-source framework for the soft error vulnerability analysis of Xilinx fpga devices. The proposed framework will allow researchers to evaluate their reliability-aware CAD algorithms and estimate the soft error susceptibility of the designs at early stages of the implementation flow for the latest Xilinx architectures.

关键词： field programmable gate arrays (fpga)

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An fpga-Based Accelerator for the 2D Implicit FDM and Its Application to Heat Conduction Simulations (Abstract Only) 15

An FPGA-Based Accelerator for the 2D Implicit FDM and Its Ap...

引用

Proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Yutaro Ishigaki Ning Li Yoichi Tomioka Akihiko Miyazaki Hitoshi Kitazawa Tokyo University of Agriculture and Technology Tokyo Japan NTT Device Technology Laboratories Kanagawa Japan

ISBN: (纸本)9781450333153

field-programmable gate arrays (fpgas) are extremely advanced with regard to high performance; they are becoming one of the primary device choices to realize high-performance computing (HPC). In this work, we propose an fpga-based accelerator for the two-dimensional (2D) finite difference method (FDM) with the implicit scheme and implement a 2D unsteady-state heat conduction simulation using red/black successive over-relaxation (SOR). The accelerator consists of a 2D single-instruction multiple-data (SIMD) array processor, which has pipelined processing elements (PEs) including 32-bit floating point calculation units. This processor can avoid the memory-access bottleneck and perform with high operating efficiency and low waiting time for data transfer by applying the proposed control method with synchronous shift data transfer. We demonstrate that the experimental hardware implemented on an Altera Stratix V fpga (5SGSMD5K2F40C2N) reaches a 99.83% operating rate of the calculation units for the computation of red/black SOR. In addition, it is approximately six times faster than GPU computing on an NVIDIA GeForce GTX 770 for a 32-bit floating-point calculation of a printed circuit board (PCB) heat conduction simulation, and it is about eight times faster than an NVIDIA Tesla C2075 for the same calculation.

关键词： 2d unsteady-state heat conduction finite difference method red/black sor 2d simd array processor parallel processing fpga

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fpga Implementation of Trained Coarse Carrier Frequency Offset Estimation and Correction for OFDM Signals (Abstract Only) 15

FPGA Implementation of Trained Coarse Carrier Frequency Offs...

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Proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Marko Jacovic James Chacko Doug Pfeil Nagarajan Kandasamy Kapil R. Dandekar Drexel University Philadelphia USA

ISBN: (纸本)9781450333153

This paper develops an fpga implementation of a trained coarse Carrier Frequency Offset estimation and correction scheme using MATLAB System Generator. The designed system is capable of supporting variable FFT sizes for Orthogonal Frequency Division Multiplexing signals and different pilot symbol structures making it compatible with a large number of wireless communication standards, unlike other work that is protocol specific. This design stands out from its more common implementations as it requires only one pilot symbol to be considered for synchronization by using a data-aided modified correlation scheme, allowing for an increase in throughput. The Bit Error Rate of the corrected signal received over an Additive White Gaussian Noise channel is compared to the case without correction. This scheme demonstrated increased performance throughput since only a single pilot symbol was used.

关键词： carrier frequency offset ofdm data-aided synchronization pilot symbol design

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Exploring Efficiency of Ring Oscillator-Based Temperature Sensor Networks on fpgas (Abstract Only) 15

Exploring Efficiency of Ring Oscillator-Based Temperature Se...

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Proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Navid Rahmanikia Amirali Amiri Hamid Noori Farhad Mehdipour Ferdowsi University of Mashhad Mashhad Iran Technical University of Munich Munich Germany Kyushu University Fukuoka Japan

ISBN: (纸本)9781450333153

Due to technology advances and complexity of designs, thermal issue is a bottleneck in electronics designs. Various dynamic thermal management techniques have been proposed to address this issue. To effectively apply thermal management techniques, providing an accurate thermal map of chips is highly required. For this goal, a network of temperature sensors ought to be provided. There are various implementations for temperature sensors and network of sensors on field programmable gate arrays (fpgas). This work defines and formulates four metrics and criteria, in terms of area, thermal, and power overheads and thermal map accuracy for exploring and evaluating efficiency of different implementations of Ring Oscillator-based Temperature Sensor (ROTS) networks on fpgas and reports the comparison results for 12 networks with various sensor configurations. According to our metrics and experiments, the sensor that it is composed of NOT gates with open latches and RNS ring counter has lower thermal and power overheads compared to other configurations. Moreover, in this work, a new ROTS is presented that occupies 25% less resources than the most compact temperature sensor. Also, it provides 1.72 times higher sensitivity than the best sensitive ROTS design.

关键词： thermal overhead fpga exploration efficiency area overhead soft-sensor ring oscillator temperature network of temperature sensor thermal map accuracy power overhead

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An Automatic Design Flow for Hybrid Parallel Computing on MPSoCs (Abstract Only) 15

An Automatic Design Flow for Hybrid Parallel Computing on MP...

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Proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Hongyuan Ding Miaoqing Huang University of Arkansas Fayetteville AR USA

ISBN: (纸本)9781450333153

State-of-the-art high-level synthesis (HLS) tools are able to lower the threshold for designers to exploit performance benefits of hardware accelerators. However, it is still a challenge to achieve parallelism on a hybrid multiprocessor system-on-chip (MPSoC). In this work, we present an automatic hybrid design flow. The hybrid hardware platform as well as both the hardware and software kernels can be generated through this flow. In addition, a hybrid OpenCL-like programming model is proposed to combine software and hardware kernels running on the unified hardware platform. Our results show that our automatic design flow can not only significantly minimize the development time, but also gain about 11 times speedup compared with pure software parallel implementation for a matrix multiplication benchmark.

关键词： hybrid and parallel computing fpga automatic design flow

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Accelerating frequent item counting with fpga 14

Accelerating frequent item counting with FPGA

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2014 acm/sigda international symposium on field programmable gate arrays, fpga 2014

作者： Sun, Yuliang Wang, Zilong Huang, Sitao Wang, Lanjun Wang, Yu Luo, Rong Yang, Huazhong E.E. Dept. TNLIST Tsinghua University China IBM Research-China China

ISBN: (纸本)9781450326711

Frequent item counting is one of the most important operations in time series data mining algorithms, and the space saving algorithm is a widely used approach to solving this problem. With the rapid rising of data input speeds, the most challenging problem in frequent item counting is to meet the requirement of wire-speed processing. In this paper, we propose a streaming oriented PE-ring framework on fpga for counting frequent items. Compared with the best existing fpga implementation, our basic PE-ring framework saves 50% lookup table resources cost and achieves the same throughput in a more scalable way. Furthermore, we adopt SIMD-like cascaded filter for further performance improvements, which outperforms the previous work by up to 3.24 times in some data distributions.

关键词： field programmable gate arrays (fpga)

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Logic gates in the routing network of fpgas (Abstract Only) 15

Logic Gates in the routing network of FPGAs (Abstract Only)

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Proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Elias Vansteenkiste Berg Severens Dirk Stroobandt Ghent University Ghent Belgium

ISBN: (纸本)9781450333153

We propose a new kind of fpga architecture with a routing network that not only provides interconnections between the functional blocks but also performs some logic operation. More specifically we replaced the routing multiplexer node in the conventional architecture with an element that can be used as both AND gate and multiplexer. A conventional routing multiplexer node consists of a multiplexer and a two stage buffer. In our new architecture a NAND gate replaces the first inverter stage of the buffer and two multiplexers half the size of the original multiplexer replace the original multiplexer. The aim of this study is to determine if this kind of architecture is feasible and if it is worth to implement pack, placement and routing tools in the future. We developed a new technology-mapping algorithm and sized the transistors in this new architecture to evaluate the area and delay. Preliminary results indicate that the gain in logic depth and area achieved by mapping to not only LUTs but also to AND gates outweighs the overhead of introducing AND gates in the routing network with a net reduction in area-delay product of 5.6. Designs implemented on the proposed architecture would require 11.2 % more area, but they will have a 14 % decreased logic depth and the architecture has a slightly faster representative critical path. These results are preliminary because the pack, place and route routines are not implemented yet.

关键词： transistor sizing technology mapping routing nodes programmable interconnection architecture logic gates

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Dynamic voltage & frequency scaling with online slack measurement 14

Dynamic voltage & frequency scaling with online slack measur...

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2014 acm/sigda international symposium on field programmable gate arrays, fpga 2014

作者： Levine, Joshua M. Stott, Edward Cheung, Peter Y. K. Department of Electrical and Electronic Engineering Imperial College London London United Kingdom

ISBN: (纸本)9781450326711

Timing margins in fpgas are already significant and as process scaling continues they will have to grow to guarantee operation under increased variation. Margins enforce worst-case operation even in typical conditions and result in devices operating more slowly and consuming more energy than necessary. This paper presents a method of dynamic voltage and frequency scaling that uses online slack measurement to determine timing headroom in a circuit while it is operating and scale the voltage and/or frequency in response. Doing so can significantly reduce power consumption or increase throughput with a minimal overhead. The method is demonstrated on a number of benchmark circuits under a range of operating conditions, constraints and optimisation targets.

关键词： field programmable gate arrays (fpga)

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Rent's rule based fpga packing for routability optimization 14

Rent's rule based FPGA packing for routability optimization

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2014 acm/sigda international symposium on field programmable gate arrays, fpga 2014

作者： Feng, Wenyi Greene, Jonathan Vorwerk, Kristofer Pevzner, Val Kundu, Arun Microsemi Corporation 3870 N 1st Street San Jose CA 95134 United States

ISBN: (纸本)9781450326711

Packing is a critical step in the CAD flow for cluster-based fpga architectures, and has a significant impact on the quality of the final placement and routing results. One basic quality metric is routability. Traditionally, minimizing cut (the number of external signals) has been used as the main criterion in packing for routability optimization. This paper shows that minimizing cut is a sub-optimal criterion, and argues to use the Rent characteristic as the new criterion for fpga packing. We further propose using a recursive bipartitioning-based k-way partitioner to optimize the Rent characteristic during packing. We developed a new packer, PPack2, based on this approach. Compared to T-VPack, PPack2 achieves 35.4%, 35.6%, and 11.2% reduction in wire length, minimal channel width, and critical path delay, respectively. These improvements show that PPack2 outperforms all previous leading packing tools (including iRAC, HDPack, and the original PPack) by a wide margin.

关键词： field programmable gate arrays (fpga)

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OmpSs@zynq all-programmable soc ecosystem

OmpSs@zynq all-programmable soc ecosystem

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2014 acm/sigda international symposium on field programmable gate arrays, fpga 2014

作者： Filgueras, Antonio Gil, Eduard Jimenez-Gonzalez, Daniel Alvarez, Carlos Martorell, Xavier Langer, Jan Noguera, Juanjo Vissers, Kees Barcelona Supercomputing Center Spain Universitat Politecnica de Catalunya Spain Xilinx Research Lab United States

ISBN: (纸本)9781450326711

OmpSs is an OpenMP-like directive-based programming model that includes heterogeneous execution (MIC, GPU, SMP, etc.) and runtime task dependencies management. Indeed, OmpSs has largely inuenced the recently appeared OpenMP 4.0 specication. Zynq All-programmable SoC combines the features of a SMP and a fpga and benets DLP, ILP and TLP parallelisms in order to eciently exploit the new tech-nology improvements and chip resource capacities. In this paper, we focus on programmability and heterogeneous ex-ecution support, presenting a successful combination of the OmpSs programming model and the Zynq All-programmable SoC platforms.

关键词： System-on-chip

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