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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是541-550 订阅

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300 Thousand gates Single Event Effect Hardened SRAM-based fpga for Space Application (Abstract Only) 15

300 Thousand Gates Single Event Effect Hardened SRAM-based F...

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Proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Lei Chen Yuanfu Zhao Zhiping Wen Jing Zhou Xuewu Li Yanlong Zhang Huabo Sun Beijing Microelectronics Technology Institute Beijing China

ISBN: (纸本)9781450333153

SRAM-based fpgas have been widely used in space engineering. However, the configuration memory in SRAM-based fpga is susceptible to the single event effects (SEE). It can disrupt the communication or control functions of the spacecraft. To mitigate SEE effects of the SRAM-based fpgas used in space radiation environment, Beijing Microelectronics Technology Institute (BMTI) developed a 300 thousand gates Single Event Effect hardened SRAM-based fpga -- BQVR300RH. The BQVR300RH employs Radiation Harden by Design (RHBD) technique. Hardened standard cell library based on Adaptive SRAM (ASRAM) structure is established. For especially sensitive and important resource, other assistant techniques are also adopted. The experiment results show that the BQVR300RH improved the anti-SEU characteristic a lot, compared with Xilinx 300 thousand gates space-grade SRAM-based fpga (XQVR300). The SEU threshold of BQVR300RH is 19.06 MeV⋅cm2/mg. The anti-SEU characteristic improves three orders of magnitude than XQVR300. The improvement of anti-SEU behavior expands the usage of SRAM-based fpga in aerospace applications. Currently, BQVR300RH has been used in space field in China.

关键词： single event upset sram-based fpga radiation harden by design

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An Embedded fpga Operating System Optimized for Vision Computing (Abstract Only) 15

An Embedded FPGA Operating System Optimized for Vision Compu...

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Proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Zhilei Chai Jin Yu Zhibin Wang Jie Zhang Haojie Zhou Jiangnan University Wuxi China State Key Laboratory of Mathematical Engineering and Advanced Computing Wuxi China

ISBN: (纸本)9781450333153

Although fpga's power and performance advantages were recognized widely, designing applications on fpga-based systems is traditionally a task undertaken by hardware experts. It is significant to allow application-level programmers with less system-level but more algorithm knowledge to realize their applications conveniently on fpgas. In this paper, an embedded fpga operating system is proposed to facilitate application-level programmers to use fpgas. Firstly, it builds specific I/Os and optimizes bus interconnection among I/Os, DDR memory, user IPs etc within the fpga for vision computing. Secondly, it manages resources of the fpga such as I/Os, DDR memory, communication etc, frees users from low-level details. Thirdly, it schedules tasks (IPs) executed on the fpga dynamically in runtime, which makes the fpga multiplexed when necessary. After porting the fpga operating system to different fpga platforms and implementing vision algorithms based on that, it shows the fpga operating system is able to simplify algorithm development on fpga platforms and improve portability of user applications. Furthermore, implementation results of several popular vision algorithms show the fpga operating system is efficient and effective for vision computing. Finally, experimental results shows that for multiple algorithms requiring more fpga resources, runtime task scheduling of multiple IPs is more efficient than a fixed IP when the SoC of fpga is considered.

关键词： vision computing operating systems portability of applications application programmers fpgas

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Memory block based scan-BIST architecture for application-dependent fpga testing 14

Memory block based scan-BIST architecture for application-de...

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2014 acm/sigda international symposium on field programmable gate arrays, fpga 2014

作者： Ito, Keita Yoneda, Tomokazu Yamato, Yuta Hatayama, Kazumi Inoue, Michiko Nara Institute of Science and Technology Nara Japan Japan Science and Technology Agency CREST Tokyo Japan

ISBN: (纸本)9781450326711

This paper presents a scan-based BIST architecture for fpgas used as application-specific embedded devices for low-volume products. The proposed architecture efficiently utilizes memory blocks, instead of logic elements, to build up BIST components such as LFSR, MISR and scan chains for test points. It also provides enhanced scan functionality for test points and performs a hybrid test application of LOC and enhanced scan to improve delay test quality. Experimental results show that the proposed BIST architecture achieves high delay test quality with efficient resource utilization.

关键词： Built-in self test

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fpga Acceleration of Irregular Iterative Computations using Criticality-Aware Dataflow Optimizations (Abstract Only) 15

FPGA Acceleration of Irregular Iterative Computations using ...

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Proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Siddhartha Nachiket Kapre Nanyang Technological University Singapore Singapore

ISBN: (纸本)9781450333153

fpga acceleration of large irregular dataflow graphs is often limited by the long tail distribution of parallelism on fine-grained overlay dataflow architectures. In this paper, we show how to overcome these limitations by exploiting criticality information along compute paths; both statically during graph pre-processing and dynamically at runtime. We statically reassociate the high-fanin dataflow chains by providing faster routes for late arriving inputs. We also perform a fanout decomposition and selective node replication in order to distribute serialization costs across multiple PEs. Additionally, we modify the dataflow firing rule in hardware to prefer critical nodes when multiple nodes are ready for dataflow evaluation. Effectively these transformations reduce the length of the tail in the parallelism profile for these large-scale graphs. Across a range of dataflow benchmarks extracted from Sparse LU factorization, we demonstrate up to 2.5× (mean 1.21×) improvement when using the static pre-processing alone, a 2.4× (mean 1.17×) improvement when using only dynamic optimizations and an overall 2.9× (mean 1.39×) improvement when both static and dynamic optimizations are enabled. These improvements are on top of 3--10× speedups over CPU implementations without our transformation enabled.

关键词： sparse graph criticality dataflow scheduling

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A Hardware Implementation of a Unit for Geometric Algebra Operations With Parallel Memory arrays (Abstract Only) 15

A Hardware Implementation of a Unit for Geometric Algebra Op...

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Proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Gerardo Soria García Adrian Pedroza de la Cruz Susana Ortega Cisneros Juan José Raygoza Panduro Eduardo Bayro Corrochano Centro de Investigación y de Estudios Avanzados del Instituto Politécnico Nacional Zapopan Mexico Centro de Investigación y de Estudios Avanzados del Instituto Politécnico Nacional zapopan Mexico Universidad de Guadalajara Guadalajara Mexico

ISBN: (纸本)9781450333153

Geometric algebra (GA) is a powerful and versatile mathematical tool which helps to intuitively express and manipulate complex geometric relationships. It has recently been used in engineering problems such computer graphics, machine vision, robotics, among others. The problem with GA in its numeric version is that it requires many arithmetic operations, and the length of the input vectors is unknown until runtime in a generic architecture operating over homogeneous elements. Few works in hardware architectures for GA were developed to improve the performance in GA applications. In this work, a hardware architecture of a unit for GA operations (geometric product) for fpga is presented. The main contribution of this work is the use of parallel memory arrays with access conflict avoidance for dealing with the issue of unknown length of input/output vectors, the intention is to reduce memory wasted when storing the input and output vectors. In this first stage of the project, we have implemented only a single access function (fixed-length) in the memory array in order to test the core of geometric product. In future works we will implement a full set of access functions with different lengths and shapes. In this work, only the simulations are presented; in the future, we will also present the experimental results

关键词： fpga address generator geometric product. geometric algebra memory arrays

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Toward Wave Digital Filter based Analog Circuit Emulation on fpga (Abstract Only) 15

Toward Wave Digital Filter based Analog Circuit Emulation on...

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Proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Wei Wu Peng Gu Yen-Lung Chen Chien-Nan Liu Sudhakar Pamarti Chang Wu Lei He University of California Los Angeles Los Angeles CA USA Tsinghua University Beijing China National Central Unviersity Jhongli Taiwan Roc Fudan University Shanghai China

ISBN: (纸本)9781450333153

Software simulation of analog and mixed-signal circuits often takes a long computing time. Unlike digital circuits that can be validated by fpga emulation, there is no winning emulation solution for analog circuits. As the first step to applying wave digital filter (WDF) to emulate post-layout analog circuits, we present how to map linear and nonlinear components in an original circuit to WDFs with exactly same behaviors. To validate, we implement the emulation circuit (i.e., WDFs) in fpga. To be more specific, each emulation time step is executed as a finite state machine, while all the computing resource, e.g. floating point units (FPU), are shared as a resource pool and used only when it is necessary, which result in a very small resource consumption on fpga. Virtually perfect match is obtained between the Verilog and SPICE simulations for a number of primitive analog circuits, indicating the high accuracy of the proposed emulation. In terms of runtime, the WDF implementation is about 3-4x faster than HSPICE on a small two-stage differential amplifier circuit. And better speedup can be anticipated when it scales to larger circuits because of the underlying binary tree structure of the WDF implementation.

关键词： wave digital filter analog circuits emulation circuit simulation fpga

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Wordwidth, instructions, looping, and virtualization the role of sharing in absolute energy minimization 14

Wordwidth, instructions, looping, and virtualization the rol...

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2014 acm/sigda international symposium on field programmable gate arrays, fpga 2014

作者： DeHon, André Department of Electrical and Systems Engineering University of Pennsylvania 200 S. 33rd St. Philadelphia PA 19104 United States

ISBN: (纸本)9781450326711

When are fpgas more energy ecient than processors? This question is complicated by technology factors and the wide range of application characteristics that can be ex-ploited to minimize energy. Using a wire-dominated en-ergy model to estimate the absolute energy required for pro-grammable computations, we determine when spatially or-ganized programmable computations (fpgas) require less energy than temporally organized programmable computa-tions (processors). The point of crossover will depend on the metal layers available, the locality, the SIMD wordwidth regularity, and the compactness of the instructions. When the Rent Exponent, p, is less than 0.7, the spatial design is always more energy ecient. When p = 0:8, the technology oers 8-metal layers for routing, and data can be organized into 16b words and processed in tight loops of no more than 128 instructions, the temporal design uses less energy when the number of LUTs is greater than 64K. We further show that heterogeneous multicontext architectures can use even less energy than the p = 0:8, 16b word temporal case.

关键词： field programmable gate arrays (fpga)

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Sequence-based In-Circuit Breakpoints for Post-Silicon Debug (Abstract Only) 15

Sequence-based In-Circuit Breakpoints for Post-Silicon Debug...

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Proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Yutaka Tamiya Yoshinori Tomita Toshiyuki Ichiba Kaoru Kawamura Fujitsu Laboratories Ltd. Kawasaki Japan

ISBN: (纸本)9781450333153

Recently, simulation and/or formal verification in pre-silicon verification cannot accomplish the whole system-level verification with exhaustive input data and run-time because of lack of sufficient speed and logic capacities. Consequently, post-silicon validation, such as in-circuit debugging, becomes increasingly important. In this paper we propose a novel breakpoint mechanism, which improves controllability of in-circuit debugging. Our contributions are summarized as follows: (1) A basic concept of a new breakpoint method is proposed, which stops the target hardware by detecting a data sequence of arbitrary length, (2) The breakpoint is shown to be implemented in an efficient pipelined hardware, which works "at-speed", in realtime and with small area overheads using CRC (Cyclic Redundancy Check), and (3) Our experimental results of detecting a data sequence in a pseudo random stream data shows that false positives can be suppressed by the CRC width and the number of sub-sequences. Since changing breakpoint conditions does not require re-implementation of the hardware, it is expected to reduce much debugging effort in post-silicon validation.

关键词： breakpoint fpga crc in-circuit debugging

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Square-rich fixed point polynomial evaluation on fpgas 14

Square-rich fixed point polynomial evaluation on FPGAs

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2014 acm/sigda international symposium on field programmable gate arrays, fpga 2014

作者： Xu, Simin Fahmy, Suhaib A. McLoughlin, Ian V. Xilinx Asia Pacific Singapore School of Computer Engineering Nanyang Technological University Singapore School of Information Science and Technology University of Science and Technology of China China

ISBN: (纸本)9781450326711

Polynomial evaluation is important across a wide range of application domains, so signicant work has been done on accelerating its computation. The conventional algorithm, referred to as Horner's rule, involves the least number of steps but can lead to increased latency due to serial com-putation. Parallel evaluation algorithms such as Estrin's method have shorter latency than Horner's rule, but achieve this at the expense of large hardware overhead. This paper presents an effcient polynomial evaluation algorithm, which reforms the evaluation process to include an increased num-ber of squaring steps. By using a squarer design that is more effcient than general multiplication, this can result in polynomial evaluation with a 57.9% latency reduction over Horner's rule and 14.6% over Estrin's method, while consuming less area than Horner's rule, when implemented on a Xilinx Virtex 6 fpga. When applied in fixed point function evaluation, where precision requirements limit the rounding of operands, it still achieves a 52.4% performance gain compared to Horner's rule with only a 4% area overhead in evaluating 5th degree polynomials.

关键词： field programmable gate arrays (fpga)

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A fpga prototype design emphasis on low power technique 14

A FPGA prototype design emphasis on low power technique

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2014 acm/sigda international symposium on field programmable gate arrays, fpga 2014

作者： Hanyang, Xu Jian, Wang Jinmei, Lai Fudan University No.825 Zhangheng Rd shanghai China

ISBN: (纸本)9781450326711

In this paper, we propose a fully-functional Nanometer fpga prototype chip. Compared to traditional single supply voltage, single threshold voltage design, we explore low power nanometer fpga design challenges with Multi-Vt, Static Voltage Scaling and sleep mode technique. Compared to Dynamic Voltage Scaling (DVS), we make a table of Voltage-Delay parameter pairs under different voltage conditions so that timing information can be calculated by a Static Timing Analysis (STA) tool. Thus a lowest supply power is chosen among all results which meet the timing requirements. This approach would simplify the hardware design since we don't need a complex workload detection circuit compared to DVS system. By separating supply voltages, we can directly shutdown power supply of the unused circuits. Compared to inserting sleep transistor in pull-up or pull-down networks, we can eliminate the speed penalty cased by the additional sleep transistor. We implement a tile-based heterogeneous architecture with island style routing and embedded specific blocks such as DSP and memory. The array size is 6431 (RowCol) including 6424 CLBs. The final design is fabricated using a 1P10M 65-nm bulk CMOS process. Test results show a 53% reduction in static power compared to a commercial fpga device which is also fabricated in 65nm process and has a similar array size.

关键词： field programmable gate arrays (fpga)

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