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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是561-570 订阅

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Optimizing effective interconnect capacitance for fpga power reduction 14

Optimizing effective interconnect capacitance for FPGA power...

引用

2014 acm/sigda international symposium on field programmable gate arrays, fpga 2014

作者： Huda, Safeen Anderson, Jason Tamura, Hirotaka Dept. of ECE University of Toronto Toronto ON Canada Fujitsu Laboratories Limited Kawasaki Japan

ISBN: (纸本)9781450326711

We propose a technique to reduce the effective parasitic capacitance of interconnect routing conductors in a bid to simultaneously reduce power consumption and improve delay. The parasitic capacitance reduction is achieved by ensuring routing conductors adjacent to those used by timing critical or high activity nets are left floating-disconnected from either VDD or GND. In doing so, the effective coupling capacitance between the conductors is reduced, because the original coupling capacitance between the conductors is placed in series with other capacitances in the circuit (series combinations of capacitors correspond to lower effective capacitance). To ensure unused conductors can be allowed to float requires the use of tri-state routing buffers, and to that end, we also propose low-cost tri-state buffer circuitry. We also introduce CAD techniques to maximize the likelihood that unused routing conductors are made to be adjacent to those used by nets with high activity or low slack, improving both power and speed. Results show that interconnect dynamic power reductions of up to 15.5% are expected to be achieved with a critical path degradation of 1%, and a total area overhead of 2.1%.

关键词： Capacitance

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Efficient Generation of Energy and Performance Pareto Front for fpga Designs (Abstract Only) 15

Efficient Generation of Energy and Performance Pareto Front ...

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Proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Sanmukh R. Kuppannagari Viktor K. Prasanna University of Southern California Los Angeles CA USA

ISBN: (纸本)9781450333153

Analysis of trade-offs between energy efficiency and latency is essential to generate designs complying with a given set of constraints. Improvements in fpga technologies offer a myriad choices for power and performance optimizations. Various algorithm intrinsic parameters also affect these objectives. The design space is compounded by the available choices. This requires efficient techniques to quickly explore the design space. Current techniques perform gate/RTL level or functional level power modeling which are slow and hence not scalable. In this work we perform efficient design space exploration using a high level performance model. We develop a semi-automatic design framework to generate energy efficiency and latency trade-offs. The framework develops a performance model given a high level specification of a design with minimal user assistance. It then explores the entire design space to generate the dominating designs with respect to energy efficiency and latency metrics. We illustrate the framework using convolutional neural network which gained significance due to its application in deep learning. We simulate a few designs from the dominating set and show that the performance estimation for the dominating designs are close to the simulated results. We also show that our framework explores 6000 design points per minute on a commodity platform such as Dell workstation as opposed to state-of-the-art techniques which explore at 50 to 60 design points per minute.

关键词： high level performance model design framework convolutional neural networks energy efficiency design space exploration

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High Level Programming of Document Classification Systems for Heterogeneous Environments using OpenCL (Abstract Only) 15

High Level Programming of Document Classification Systems fo...

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Proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Nasibeh Nasiri Oren Segal Martin Margala Wim Vanderbauwhede Sai Rahul Chalamalasetti University of Massachusetts Lowell Lowell MA USA University of Glasgow Glasgow United Kingdom HP Servers Houston TX USA

ISBN: (纸本)9781450333153

Document classification is at the heart of several of the applications that have been driving the proliferation of the internet in our daily lives. The ever growing amounts of data and the need for higher throughput, more energy efficient document classification solutions motivated us to investigate alternatives to the traditional homogenous CPU based implementations. We investigate a heterogeneous system where CPUs are combined with fpgas as system accelerators. Incorporating fpgas as accelerators in a heterogeneous computing environment allows for the creation of flexible custom hardware solutions that can potentially offer increased power efficiency and performance gains. One of the main issues delaying wide spread adoption of fpgas as standard heterogeneous system accelerators is the difficulty in programming them. The OpenCL standard offers a unified C programming model for any device that adheres to its standards. An Altera OpenCL fpga based implementation of a document classification system is investigated in which a stream of HTML documents is scored according to a profile on a document-by-document basis. The results show that the throughput of the document classification application with and without Bloom Filters is 312MB/s and 343MB/s respectively, when running on CPU, and 354MB/s and 452MB/s respectively, when running on an fpga. Our results also show up to 32% power efficiency improvement for the fpga implementation over the CPU implementation. We would like to thank Davor Capalija from Altera for his invaluable advice during our work on the fpga version of the algorithm.

关键词： heterogeneous computing high throughput bloom filter filtering system opencl fpga document classification

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Towards interconnect-adaptive packing for fpgas 14

Towards interconnect-adaptive packing for FPGAs

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2014 acm/sigda international symposium on field programmable gate arrays, fpga 2014

作者： Luu, Jason Rose, Jonathan Anderson, Jason Dept. Electrical and Computer Engineering University of Toronto Toronto ON Canada

ISBN: (纸本)9781450326711

In order to investigate new fpga logic blocks, fpga ar-chitects have traditionally needed to customize CAD tools to make use of the new features and characteristics of those blocks. The software development effort necessary to cre-ate such CAD tools can be a time-consuming process that can significantly limit the number and variety of architec-tures explored. Thus, architects want flexible CAD tools that can, with few or no software modifications, explore a diverse space. Existing flexible CAD tools suffer from im-practically long runtimes and/or fail to efficiently make use of the important new features of the logic blocks being in-vestigated. This work is a step towards addressing these concerns by enhancing the packing stage of the open-source VTR CAD flow [17] to efficiently deal with common inter-connect structures that are used to create many kinds of use-ful novel blocks. These structures include crossbars, carry chains, dedicated signals, and others. To accomplish this, we employ three techniques in this work: speculative packing , pre-packing, and interconnect-aware pin counting. We show that these techniques, along with three minor modi-fications, result in improvements to runtime and quality of results across a spectrum of architectures, while simultane-ously expanding the scope of architectures that can be ex-plored. Compared with VTR 1.0 [17], we show an average 12-fold speedup in packing for fracturable LUT architectures with 20% lower minimum channel width and 6% lower crit-ical path delay. We obtain a 6 to 7-fold speedup for archi-tectures with non-fracturable LUTs and architectures with depopulated crossbars. In addition, we demonstrate packing support for logic blocks with carry chains.

关键词： field programmable gate arrays (fpga)

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Real-Time Obstacle Avoidance for Mobile Robots via Stereoscopic Vision Using Reconfigurable Hardware (Abstract Only) 15

Real-Time Obstacle Avoidance for Mobile Robots via Stereosco...

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Proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Martinianos Papadopoulos Christos Ttofis Christos Kyrkou Theocharis Theocharides University of Cyprus Nicosia Cyprus ACC Innovations Ltd Nicosia Cyprus

ISBN: (纸本)9781450333153

An embedded, real-time, and low power obstacle avoidance system is a critical component towards fully autonomous robots that can be used in safety missions, space exploration, and transportation systems among others. In this paper a complete prototyping platform for the evaluation of obstacle avoidance systems and autonomous robots is realized on reconfigurable hardware. An efficient stereo vision algorithm for producing the necessary 3D and an obstacle avoidance subsystem were both implemented on an ATLYS Spartan-6 fpga board equipped with a VmodCam stereo camera module. A modified FDX Vantage 1/10 electric car platform was used for testing the proposed architecture in indoor and outdoor real-world scenes. The system receives stereo image data from the VmodCam module and a decision-making algorithm is applied on a specified Region of Interest (RoI) on the produced disparity map. The algorithm outputs the direction that the robot should move to in order to avoid any obstacles present. Experimental evaluation results indicate that the fpga-based robotic platform can avoid obstacles in real-time (i.e. can process and identify obstacles within a 1/30th of a second that a stereo image takes to be processed) in both indoor and outdoor environments, with 91.7% accuracy, equivalent to software implementations. The overall power consumption of the proposed architecture, excluding the electronic car platform, is 6 W, making it ideal for use on mobile robots, without becoming a significant drain on its battery life.

关键词： stereoscopic vision fpga obstacle avoidance hardware based autonomous navigation

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An Efficient and Flexible fpga Implementation of a Face Detection System (Abstract Only) 15

An Efficient and Flexible FPGA Implementation of a Face Dete...

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Proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Hichem Ben Fakih Ahmed Elhossini Ben Juurlink Technical University of Berlin Berlin Germany

ISBN: (纸本)9781450333153

Robust and rapid face detection systems are constantly gaining more interest, since they represent the first stone for many challenging tasks in the field of computer vision. In this paper a software-hardware co-design approach is presented, that enables the detection of frontal faces in real time. A complete hardware implementation of all components taking part of the face detection is introduced. This work is based on the object detection framework of Viola and Jones, which makes use of a cascade of classifiers to reduce the computation time. The proposed architecture is flexible, as it allows the use of multiple instances of the face detector. This makes developers free to choose the speed range and reserved resources for this task. The current implementation runs on the Zynq SoC and receives images over IP network, which allows exposing the face detection task as a remote service that can be consumed from any device connected to the network. We performed several measurements for the final detector and the software equivalent. Using three Evaluator cores, the ZedBoard system achieves a maximal average frame rate of 13.4 FPS when analysing an image containing 640x480 pixels. This stands for an improvement of 5.25 times compared to the software solution and represents acceptable results for most real-time systems. On the ZC706 system, a higher frame rate of 16.58 FPS is achieved. The proposed hardware solution achieved 92% accuracy, which is low compared to the software solution (97%) due to different scaling algorithm. The proposed solution achieved higher frame rate compared to other solutions found in the literature.

关键词： face detection fpga viola and jones copmuter visioin zynq

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Silicon Verification using High-Level Design Tools (Abstract Only) 15

Silicon Verification using High-Level Design Tools (Abstract...

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Proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Tomasz S. Czajkowski Altera Corporation Toronto Canada

ISBN: (纸本)9781450333153

Modern fpgas comprise ever more complex blocks to enable a wide variety of customer applications. Verification of the complex blocks can be a time consuming process, especially at the late stages of the release cycle. A key challenge is the time it takes to create circuits that can run on a target device to test a given block. This paper demonstrates how High-Level Design tools, such as Altera SDK for OpenCL, can be utilized to aid in this work to verify the operation of complex hardened blocks. As a proof of concept, we present the methodology used to verify the correctness of hardened single-precision floating point adder, subtractor and multiplier units on Altera Arria 10 fpga in a single day. Each design comprised an instance of a hardened floating point unit, either an adder, subtractor or a multiplier, and a functional equivalent there of implemented purely using Lookup Tables (LUTs). Both the hardened module instance and the LUT implementation were generated from OpenCL description using Altera SDK for OpenCL. The results for each computation were compared between the two implementations and any single discrepancy constituted a test failure. To simplify the test, the I/O for each design comprised LEDs (for pass/fail/running/done status) and two switches -- start and reset. The test design for adder, subtractor and a multiplier were all written in OpenCL, the compilation of each design took approximately 30 minutes for each test design. Each design tested 4 billion test vectors, generated on-chip using a Mersenne Twister, and each test completed within 30 seconds. All tests passed verification in hardware.

关键词： floating point fpga dsp blocks

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Single-Loop Approach to 2-D Wavelet Lifting with JPEG 2000 Compatibility

Single-Loop Approach to 2-D Wavelet Lifting with JPEG 2000 C...

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international symposium on Computer Architecture and High Performance Computing Workshops (SBAC-PADW)

作者： David Barina Petr Musil Martin Musil Pavel Zemcik Brno University of Technology Czech Republic

A novel approach to 2-D single-loop wavelet lifting with compatibility to JPEG 2000 is presented in this paper. A newly developed 2-D core of CDF 5/3 wavelet filter is presented that, using a new sequence of operations, simplify the design. Moreover, the proposed approach, that uses one pass for 2-D transform, directly produces final output and reduces significantly the need for storing intermediate results into memory. All the proposed structures can be efficiently pipelined in hardware. This paper describes the proposed approach, its implementation in fpga, cost of such implementation, and brings an experimental evaluation as well as discussion of the features of the approach.

关键词： Transform coding Discrete wavelet transforms field programmable gate arrays Computer architecture Image coding

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A Parallel And Scalable Multi-fpga based Architecture for High Performance Applications (Abstract Only) 15

A Parallel And Scalable Multi-FPGA based Architecture for Hi...

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Proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Venkatasubramanian Viswanathan Rabie Ben Atitallah Jean-Luc Dekeyser Benjamin Nakache Maurice Nakache Nolam Embedded Systems Paris France University of Valenciennes Valenciennes France University of Lille 1 Lille France Nolam Embedded Systems Pariis France

ISBN: (纸本)9781450333153

Several industrial applications are becoming highly sophisticated and distributed as they capture and process real-time data from several sources at the same time. Furthermore, availability of acquisition channels such as I/O interfaces per fpga, also dictates how applications are partitioned over several devices. Thus computationally intensive, resource consuming functions are implemented on multiple hardware accelerators, making low-latency communication to be a crucial factor. In such applications, communication between multiple devices means using high-speed point-to-point protocols with little flexibility in terms of communication scalability. The problem with the current systems is that, they are usually built to meet the needs of a specific application, i.e., lacks flexibility to change the communication topology or upgrade hardware resources. This leads to obsolescence, hardware redesign cost, and also wastes computing power. Taking this into consideration, we propose a scalable, modular and customizable computing platform, with a parallel full-duplex communication network, that redefines the computation and communication paradigm in such applications. We have implemented a scalable distributed secure H.264 encoding application with 3 channels over 3 customizable fpga modules. In a distributed architecture, the inter-fpga communication time is almost completely overshadowed by the overall execution time for bigger data-sets, and is comparable to the overall execution time of a non-distributed architecture, for the same implementation scaled down to 1 channel for 1 fpga. This makes our architecture highly scalable and suitable for high-performance streaming applications. With 3 detachable fpga modules, each sending and receive data simultaneously at 3 GB/s each, we measured the total net unidirectional traffic at any given time in the system is 9 GB/s, making the total net bidirectional bandwidth for 6 modules to be 36 GB/s.

关键词： scalable system parallel reconfigurable architecture distributed intensive signal processing

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fpga-based biophysically-meaningful modeling of olivocerebellar neurons 14

FPGA-based biophysically-meaningful modeling of olivocerebel...

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2014 acm/sigda international symposium on field programmable gate arrays, fpga 2014

作者： Smaragdos, Georgios Isaza, Sebastian Van Eijk, Martijn Sourdis, Ioannis Strydis, Christos Dept. of Neuroscience Erasmus Medical Center Rotterdam Netherlands Dept. de Ingeniería Electrónica Universidad de Antioquia UdeA Medellín Colombia Faculty of Electrical Engineering Mathematics and Computer Science Delft University of Technology Delft Netherlands Dept. of Computer Science and Engineering Chalmers University of Technology Gothenburg Sweden

ISBN: (纸本)9781450326711

The Inferior-Olivary nucleus (ION) is a well-charted region of the brain, heavily associated with sensorimotor control of the body. It comprises ION cells with unique properties which facilitate sensory processing and motor-learning skills. Various simulation models of ION-cell networks have been written in an attempt to unravel their mysteries. However, simulations become rapidly intractable when biophysically plausible models and meaningful network sizes (100 cells) are modeled. To overcome this problem, in this work we port a highly detailed ION cell network model, originally coded in Matlab, onto an fpga chip. It was first converted to ANSI C code and extensively profiled. It was, then, translated to HLS C code for the Xilinx Vivado toolflow and various algorithmic and arithmetic optimizations were applied. The design was implemented in a Virtex 7 (XC7VX485T) device and can simulate a 96-cell network at real-time speed, yielding a speedup of 700 compared to the original Matlab code and 12.5 compared to the reference C implementation running on a Intel Xeon 2.66GHz machine with 20GB RAM. For a 1,056-cell network (non-real-time), an fpga speedup of 45 against the C code can be achieved, demonstrating the design's usefulness in accelerating neuroscience research. Limited by the available on-chip memory, the fpga can maximally support a 14,400-cell network (non-real-time) with online parameter configurability for cell state and network size. The maximum throughput of the fpga IONnetwork accelerator can reach 2.13 GFLOPS.

关键词： Neural networks

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