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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是581-590 订阅

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Methodology to generate multi-dimensional systolic arrays for fpgas using openCL (abstract only) 14

Methodology to generate multi-dimensional systolic arrays fo...

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Proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Nick Ni Embedded Applications Engineer Altera Corporation San Jose CA USA

ISBN: (纸本)9781450326711

Systolic arrays (SA) in a fpga provide a significant speed up on many scientific calculations through massive parallelism exploitation. The low-level hardware design of such complex SA is becoming more time-consuming and non-scalable with more transistors being available on a single chip. In this paper we present a novel methodology to generate multi-dimensional SA for fpgas using a well-accepted high-level language, OpenCL. Kernels written in OpenCL can then be compiled directly into hardware using an OpenCL high-level synthesis tool. A complex case study using our methodology is presented. We were able to design, generate, verify and optimize the entire fpga based hardware accelerator using the Smith-Waterman, in only three man weeks. The accelerator's top performance was 32.6 GCUPS (Giga-Cell-Updates-Per-Second) on a DNA similarity search with 1.3 GCUPS/watt efficiency. The result is superior to most state-of-the-art CPU/GPU implementations and competitive against a hand-crafted hardware design which took many months to develop.

关键词： high-level synthesis bioinformatics productivity smith-waterman opencl fpga systolic arrays generation algorithm

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A new basic logic structure for data-path computation (abstract only) 14

A new basic logic structure for data-path computation (abstr...

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Proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Pierre-Emmanuel Gaillardon Luca Amarù Giovanni De Micheli Swiss Federal Institute of Technology Lausanne Switzerland

ISBN: (纸本)9781450326711

Nowadays, field programmable gate arrays (fpga) implement arithmetic functions using specific circuits at the logic block level, such as the carry paths, or at the structure level adopting Digital Signal Processing (DSP) blocks. Nevertheless, all these approaches, introduced to ease the realization of specific functions, are lacking of generality. In this paper, we introduce a new logic block that natively realizes arithmetic functions while preserving the versatility to implement general logic functions. It consists of a partially interconnected matrix of signal routers driven by comparators. We demonstrate that this structure can realize (i) any 2-output 2-input logic function or (ii) any single-output 3-input logic function or (iii) specific logic, such as arithmetic functions, with up to 4-output and 8-inputs. As compared to a standard 6-input Look Up Table (LUT), the proposed block requires roughly the same area but is 35.3% faster. Even though the proposed block has not the same exhaustive configurability of a 6-input LUT, there are arithmetic functions realizable in a single block that do not fit in one, or even more, 6-input LUT. For example, a single block inherently implements an entire 3-bit adder that requires 3× more resources with LUTs plus also custom circuitry. From a system level perspective, we show that a 256-bit adder is implemented with a gain on area×delay product of 31% as compared to its traditional LUT-based counterpart.

关键词： arithmetic functions logic element fpga bbdd

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fpga LUT design for wide-band dynamic voltage and frequency scaled operation (abstract only) 14

FPGA LUT design for wide-band dynamic voltage and frequency ...

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Proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Monther Abusultan Sunil P. Khatri Texas A&M University College Station TX USA

ISBN: (纸本)9781450326711

field programmable gate arrays (fpgas) are the implementation platform of choice when it comes to design flexibility. However, the high power consumption of fpgas (which arises due to their flexible structure), make them less appealing for extreme low power applications. In this paper, we present a design of an fpga look-up table (LUT), with the goal of seamless operation over a wide band of supply voltages. The same LUT design has the ability to operate at sub-threshold voltage when low power is required, and at higher voltages whenever faster performance is required. The results show that operating the LUT in sub-threshold mode yields a (~80x) lower power and (~4x) lower energy than full supply voltage operation, for a 6-input LUT implemented in a 22nm predictive technology. The key drawback of sub-threshold operation is its susceptibility to process, temperature, and supply voltage (PVT) variations. This paper also presents the design and experimental results for a closed-loop adaptive body biasing mechanism to dynamically cancel these PVT variations. For the same 22nm technology, we demonstrate that the closed-loop adaptive body biasing circuits can allow the fpga to operate over an operating frequency range that spans an order of magnitude (40 MHz to 1300 MHz). We also show that the closed-loop adaptive body biasing circuits can cancel delay variations due to supply voltage changes, and reduce the effect of process variations on setup and hold times by 1.8x and 2.9x respectively.

关键词： low power dynamic body bias lut fpga subthreshold dvfs pvt variation cancellation

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Pushing the performance boundary of linear projection designs through device specific optimisations (abstract only) 14

Pushing the performance boundary of linear projection design...

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Proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Rui Policarpo Duarte Christos-Savvas Bouganis Imperial College London London United Kingdom

ISBN: (纸本)9781450326711

The continuous scaling of the fabrication process combined with the ever increasing need of high performance designs, means that the era of treating all devices the same is about to come to an end. The presented work considers device oriented optimisations in order to further boost the performance of a Linear Projection design by focusing on the over-clocking of arithmetic operators. A methodology is proposed for the acceleration of Linear Projection designs on an fpga, that introduces information about the performance of the hardware under over-clocking conditions to the application level. The novelty of this method is a pre-characterisation of the most prone to error arithmetic operators and the utilisation of this information in the high-level optimization process of the design. This results in a set of circuit designs that achieve higher throughput with minimum error. fpga devices are suitable for such optimisations due to their reconfigurability feature that allows performance characterisation of the underlying fabric prior to the design of the final system. The reported results show that significant gains in the performance of the system can be achieved, i.e. up to 1.85 times speed up in the throughput compared to existing methodologies, when such device specific optimisation is considered.

关键词： fpga device characterisation over-clocking linear projection

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Using DSP blocks to compute CRC hash in fpga (abstract only) 14

Using DSP blocks to compute CRC hash in FPGA (abstract only)

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Proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Viktor Puš Lukáš Kekely Tomáš Závodník CESNET Prague Czech Rep

ISBN: (纸本)9781450326711

Hash table and its variations are common ways to implement lookup operations in fpga. The process of adding to, deleting from, and searching in the hash table uses one or more hash functions to compute the address to the table. A suitable hash function must meet statistical properties such as uniform distribution, use of all input bits, large change of output based on small change of input. Other desirable parameters are high throughput and low fpga resources usage. We propose a novel approach to the CRC hash computation in fpga. The method is suitable for applications such as hash tables, which use parallel inputs of fixed size and require high throughput. We employ DSP blocks present in modern fpgas to perform all the necessary XOR operations, therefore our solution does not use any LUTs. We propose a Monte Carlo based heuristic to reduce the number of DSP blocks required. Our experimental results show that one DSP block capable of 48 XOR operations can replace around eleven 6-input LUTs. Our results further show that our solution performs less XOR operations than the solution with LUTs optimized by the synthesizer.

关键词： hash fpga dsp crc

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Improving bitstream compression by modifying fpga architecture 13

Improving bitstream compression by modifying FPGA architectu...

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2013 acm/sigda international symposium on field programmable gate arrays, fpga 2013

作者： Razavi, Seyyed Ahmad Saheb Zamani, Morteza Department of Computer Engineering and Information Technology Amirkabir University of Technology Tehran Iran

ISBN: (纸本)9781450318877

The size of configuration bitstreams of field-programmable gate arrays (fpga) is increasing rapidly. Compression techniques are used to decrease the size of bitstreams. In this paper, an appropriate bitstream format and variable symbol lengths are proposed to utilize the routing patterns for enhancing the compression efficiency. An order of inputs of multiplexers in switch modules is also proposed to improve the symbol statistics and hence, the compression efficiency. A framework to generate the bitstream and hardware description of fpgas is developed as well. Experimental results over 20 MCNC benchmarks show that by applying the proposed approaches, the compression rate is improved by 46% on average compared to the methods with fixed symbol lengths without any area and performance degradation. © 2013 acm.

关键词： field programmable gate arrays (fpga)

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On energy efficiency and amdahl's law in fpga based chip heterogeneous multiprocessor systems (abstract only) 14

On energy efficiency and amdahl's law in FPGA based chip het...

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Proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Sen Ma David Andrews University of Arkansas Fayetteville AR USA

ISBN: (纸本)9781450326711

This poster presents our preliminary findings on the relationship between speedup and energy efficiency on fpga based Chip Heterogeneous Multiprocessor Systems (CHMPs). While researchers have investigated how to tailor combinations of heterogeneous compute engines within a CHMP system to best meet the performance needs of specific applications, exploring how these optimized architectures also effect energy efficiency is not as well studied. We show that a simple relationship exists between the speedup these systems gain and their associated energy efficiency. We show that the simple relationship between Amdahl's law and energy efficiency. All the experiments result achieved through actual run time measurements on homogeneous and heterogeneous multiprocessor systems implemented within a Xilinx Virtex6 fpga. We further show how a systems with 6 MicroBlaze soft processors' dynamic power and hence the overall energy efficiency of the system can be effected through transparent operating system control of the compute resources. We also present how to use clock gating to control the dynamic power consumption for each processor and with this careful power-aware management unit, the system's dynamic power consumption can follow the requirements of each application.

关键词： power-optimization algorithm reconfigurable computing dynamic power

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Novel fpga clock network with low latency and skew (abstract only) 14

Novel FPGA clock network with low latency and skew (abstract...

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Proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Lei Li Jian Wang Jinmei Lai State Key Laboratory of ASIC and System Fudan University Shanghai China

ISBN: (纸本)9781450326711

Clock network is a dedicated network for distributing multiple clock signals to every logic modules in a system. Be significantly different from ASIC where the clock tree is custom built by users, clock network in fpga is usually fixed after chip fabrication and cannot be changed for different user circuits. This paper is committed to design and implement fpga clock network with low latency and skew. We first propose a novel clock network for FPG, which is a backbone-branches topology and can be easily integrated to the tiled fpga with reasonable area. There are one clock backbone and several primary clock branches in the network. When the chip scales up, this clock network can be extended easily. Afterwards, series of strategies such as hybrid multiplexer, bypassing, looping back and programmable Delay Adjustment Unit (DAU) are employed to optimize latency and skew. Moreover, the prominent couple capacitance and crosstalk effect of clock routing in nanometer are also given consideration in physical implementation. This clock network is applied to own-designed fpga with 65nm technology. Post-layout simulation results indicate that our clock network with normal loads can uphold 600MHz clock with the maximum clock latency and skew being typically 2.22ns and 40ps respectively, 1.79ns and 39ps in the fast case, achieving up to 78.2% improvement for skew as well as 47.5% for latency, compared to a commercial 65nm fpga device.

关键词： dau fpga latency clock network skew

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Future inter-fpga communication architecture for multi-fpga based prototyping (abstract only) 14

Future inter-FPGA communication architecture for multi-FPGA ...

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Proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Qingshan Tang Matthieu Tuna Habib Mehrez Université Pierre et Marie CURIE Paris France Flexras Technologies Paris France

ISBN: (纸本)9781450326711

Multi-fpga boards are widely used for rapid system prototyping. Even though the prototyping is trying to reach the maximum performance, the performance is limited by the inter-fpga communication. As the capacity per I/O for each fpga generation is increasing, fpga I/Os are becoming a scarce resource. The design is divided into several parts, each part's capacity fits in a single fpga. Signals crossing design's parts located in different fpgas are called cut nets. In order to resolve pin limitation problem, cut nets are sent between fpgas in pipelined way using the Time-Division-Multiplexing technique. The maximum number of cut nets passing through one fpga I/O is called the TDM ratio. There are two multiplexing architectures used for multi-fpga based prototyping: Logic Multiplexing and ISERDES/OSERDES. In this paper, a new multiplexing architecture Multi-Gigabit Transceiver (MGT) is proposed. Experiments are done in a multi-fpga board with the testbench LFSR to validate the achieved performance. Assume that all the fpga I/Os used for inter-fpga communication are MGT capable in the future. Analyses show that the proposed multiplexing architecture can achieve higher performance when the TDM ratio exceeds 67. The gain in performance of the proposed architecture over the existing architecture augments as the TDM ratio increases.

关键词： multi-fpga based prototyping logic multiplexing inter-fpga communication iserdes/oserdes multi-gigabit transceiver

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A remote memory access infrastructure for global address space programming models in fpgas 13

A remote memory access infrastructure for global address spa...

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2013 acm/sigda international symposium on field programmable gate arrays, fpga 2013

作者： Willenberg, Ruediger Chow, Paul Dept. of Electrical and Computer Engineering University of Toronto Toronto ON Canada

ISBN: (纸本)9781450318877

We are proposing a shared-memory communication infrastructure that provides a common parallel programming interface for fpga and CPU components in a heterogeneous system. Our intent is to ease the integration of reconfigurable hardware into parallel programming models like Partitioned Global Address Space (PGAS). For this purpose, we introduce a remote memory access component based on Active Messages that implements the core API of the Berkeley GASNet communication library, and a simple controller that manages communication and synchronization for custom fpga cores. We demonstrate how these components deliver a simple and easily configurable communication mechanism between distributed memories in a multi-fpga system with processors as well as custom hardware nodes. © 2013 acm.

关键词： field programmable gate arrays (fpga)

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