检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,335 篇 会议
41 篇 期刊文献

馆藏范围

1,376 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

811 篇 工学
- 784 篇 计算机科学与技术...
- 348 篇 软件工程
- 281 篇 电气工程
- 259 篇 电子科学与技术（可...
- 122 篇 信息与通信工程
- 36 篇 动力工程及工程热...
- 35 篇 控制科学与工程
- 30 篇 机械工程
- 17 篇 生物工程
- 14 篇 仪器科学与技术
- 12 篇 建筑学
- 12 篇 土木工程
- 10 篇 生物医学工程（可授...
- 9 篇 冶金工程
- 8 篇 化学工程与技术
- 7 篇 光学工程
- 7 篇 材料科学与工程（可...
- 3 篇 农业工程
224 篇 理学
- 184 篇 数学
- 36 篇 物理学
- 20 篇 统计学（可授理学、...
- 19 篇 生物学
- 11 篇 系统科学
- 7 篇 化学
62 篇 管理学
- 50 篇 管理科学与工程(可...
- 34 篇 工商管理
- 13 篇 图书情报与档案管...
16 篇 经济学
- 16 篇 应用经济学
11 篇 法学
- 9 篇 社会学
3 篇 农学
- 3 篇 作物学
2 篇 教育学
1 篇 医学

主题

451 篇 fpga
269 篇 field programmab...
171 篇 field programmab...
27 篇 high-level synth...
26 篇 reconfigurable c...
22 篇 deep learning
22 篇 opencl
20 篇 computer archite...
18 篇 hls
18 篇 routing
18 篇 hardware acceler...
18 篇 hardware
17 篇 fpgas
16 篇 accelerator
16 篇 placement
14 篇 neural networks
14 篇 cnn
14 篇 machine learning
14 篇 convolutional ne...
13 篇 clocks

机构

19 篇 university of ca...
12 篇 tsinghua univers...
12 篇 fudan university
12 篇 imperial college...
11 篇 university of to...
10 篇 peking universit...
10 篇 university of to...
9 篇 university of ce...
9 篇 university of so...
8 篇 univ of californ...
7 篇 university of sc...
7 篇 univ of toronto ...
7 篇 epfl lausanne
7 篇 école polytechni...
7 篇 univ toronto dep...
7 篇 nanyang technolo...
7 篇 tsinghua univ pe...
6 篇 univ british col...
6 篇 univ calif los a...
6 篇 northeastern uni...

作者

37 篇 cong jason
26 篇 rose jonathan
22 篇 jason cong
17 篇 betz vaughn
15 篇 zhang zhiru
14 篇 chen deming
13 篇 ienne paolo
12 篇 chow paul
12 篇 wawrzynek john
11 篇 hauck scott
10 篇 dehon andré
10 篇 luk wayne
10 篇 prasanna viktor ...
10 篇 langhammer marti...
9 篇 jinmei lai
9 篇 anderson jason h...
9 篇 wilton steven j....
9 篇 schmit herman
9 篇 jonathan rose
9 篇 constantinides g...

语言

1,356 篇 英文
19 篇 其他
1 篇 中文

检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是601-610 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Architectural enhancements in Stratix V™ 13

Architectural enhancements in Stratix V™

引用

2013 acm/sigda international symposium on field programmable gate arrays, fpga 2013

作者： Lewis, David Cashman, David Chan, Mark Chromczak, Jeffery Lai, Gary Lee, Andy Vanderhoek, Tim Yu, Haiming Altera Corporation 101 Innovation Drive San Jose CA 95134 United States Altera Corporation 150 Bloor St W. Toronto ON M5S 2X9 Canada

ISBN: (纸本)9781450318877

This paper describes architectural enhancements in the Altera Stratix-V" fpga architecture, built on a 28nm TSMC process, together with the data supporting those choices. Among the key features are time borrowing flip-flops, a doubling of the number of flip-flops per LUT compared to previous Stratix architectures, a simplified embedded 20kb dual-port RAM block, and error correction that can correct up to 8 adjacent errors. Arithmetic performance is significantly improved using a fast adder with two levels of multi-bit skip. We also describe how the routing architecture and layout is optimized for the 28nm process to take advantage of a wider range of wire thicknesses offered on the different layers, and improvements in performance and routability are obtained without dramatic changes to the repeated floorplan of the logic plus routing fabric. © 2013 acm.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

High-level synthesis with LegUp: A crash course for users and researchers 13

High-level synthesis with LegUp: A crash course for users an...

引用

2013 acm/sigda international symposium on field programmable gate arrays, fpga 2013

作者： Anderson, Jason H. Brown, Stephen D. Canis, Andrew Choi, Jongsok Department of Electrical and Computer Engineering University of Toronto Toronto ON Canada

ISBN: (纸本)9781450318877

High-level synthesis (HLS) has been gaining traction recently as a design methodology for fpgas, with the promise of raising the productivity of fpga hardware designers, and ultimately, opening the door to the use of fpgas as computing devices targetable by software engineers. In this tutorial, we introduce LegUp, an open-source HLS tool for fpgas developed at the University of Toronto. With LegUp, a user can compile a C program completely to hardware, or alternately, he/she can choose to compile the program to a hybrid hardware/software system comprising a processor along with one or more accelerators. LegUp supports the synthesis of most of the C language to hardware, including loops, structs, multi-dimensional arrays, pointer arithmetic, and floating point operations. The LegUp distribution includes the CHStone HLS benchmark suite, as well as a test suite and associated infrastructure for measuring quality of results, and for verifying the functionality of LegUp-generated circuits. LegUp is freely downloadable at ***, providing a powerful platform that can be leveraged for new high-level synthesis research. © 2013 Authors.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

Sensing nanosecond-scale voltage attacks and natural transients in fpgas 13

Sensing nanosecond-scale voltage attacks and natural transie...

引用

2013 acm/sigda international symposium on field programmable gate arrays, fpga 2013

作者： Zick, Kenneth M. Srivastav, Meeta Zhang, Wei French, Matthew Arlington VA United States Virginia Tech. Blacksburg VA United States University of Virginia Charlottesville VA United States

ISBN: (纸本)9781450318877

Voltage noise not only detracts from reliability and performance, but has been used to attack system security. Most systems are completely unaware of fluctuations occurring on nanosecond time scales. This paper quantifies the threat to fpga-based systems and presents a solution approach. Novel measurements of transients on 28nm fpgas show that extreme activity in the fabric can cause enormous undershoot and overshoot, more than 10× larger than what is allowed by the specification. An existing voltage sensor is evaluated and shown to be insufficient. Lastly, a sensor design using reconfigurable logic is presented;its time-to-digital converter enables sample rates 500× faster than the 28nm Xilinx ADC. This enables quick characterization of transients that would normally go undetected, thereby providing potentially useful data for system optimization and helping to defend against supply voltage attacks. © 2013 acm.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

Improving the security and the scalability of the AES algorithm (abstract only) 14

Improving the security and the scalability of the AES algori...

引用

Proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Alessandro A. Nacci Vincenzo Rana Marco D. Santambrogio Donatella Sciuto Politecnico di Milano Milano Italy

ISBN: (纸本)9781450326711

Although the reliability and robustness of the AES protocol have been deeply proved through the years, recent research results and technology advancements are rising serious concerns about its solidity in the (quite near) future. In fact, smarter brute force attacks and new computing systems are expected to drastically decrease the security of the AES protocol in the coming years (e.g., quantum computing will enable the development of search algorithms able to perform a brute force attack of a 2n-bit key in the same time required by a conventional algorithm for a n-bit key). In this context, we are proposing an extension of the AES algorithm in order to support longer encryption keys (thus increasing the security of the algorithm itself). In addition to this, we are proposing a set of parametric implementations of this novel extended protocols. These architectures can be optimized either to minimize the area usage or to maximize their performance. Experimental results show that, while the proposed implementations achieve a throughput higher than most of the state-of-the-art approaches and the highest value of the Performance/Area metric when working with 128-bit encryption keys, they can achieve a 84× throughput speedup when compared to the approaches that can be found in literature working with 512-bit encryption keys.

关键词： fpga advanced ecryption standard cryptography security aes

来源：评论

学校读者我要写书评

暂无评论

Placement of repair circuits for in-field fpga repair 13

Placement of repair circuits for in-field FPGA repair

引用

2013 acm/sigda international symposium on field programmable gate arrays, fpga 2013

作者： Wirthlin, Michael Jensen, Josh Wilson, Alex Howes, Will Wen, Shi-Jie Wong, Rick Dept. of Electrical and Computer Engineering Brigham Young University Provo UT 84606 United States Cisco Systems San Jose CA 95134 United States

ISBN: (纸本)9781450318877

With the growing density and shrinking feature size of modern semiconductors, it is increasingly difficult to manufacture defect free semiconductors that maintain acceptable levels of reliability for long periods of time. These systems are increasingly susceptible to wear-out by failing to meet their operational specifications for an extended period of time. The reconfigurability of fpgas can be used to repair post-manufacturing faults by configuring the fpga to avoid a damaged resource. This paper presents a method for repairing fpga devices with wear-out faults by precomputing a set of repair circuits that, collectively, can repair a fault found in any logic block of the fpga. This approach relies on logic placement to create "repair" circuits that avoid specific logic blocks. Three repair placement algorithms will be presented that generate a complete set of repair designs during the conventional placement process. The number of repairs needed to create a complete repair set depends heavily on the utilization of the fpga resources. The three algorithms are tested against several benchmarks and with multiple area constraints for each benchmark. The best repair placement approach described in the paper generates a full set of repair circuits at a computation cost of 16X that of a conventional placer and with circuits of comparable quality. © 2013 acm.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

Fully-functional fpga prototype with fine-grain programmable body biasing 13

Fully-functional FPGA prototype with fine-grain programmable...

引用

2013 acm/sigda international symposium on field programmable gate arrays, fpga 2013

作者： Hioki, Masakazu Sekigawa, Toshihiro Nakagawa, Tadashi Koike, Hanpei Matsumoto, Yohei Kawanami, Takashi Tsutsumi, Toshiyuki Tsukuba Japan Tokyo University of Marine Science and Technology Tokyo Japan Kanazawa Institute of Technology Kanazawa Japan Meiji University Kawasaki Japan

ISBN: (纸本)9781450318877

A fully-functional fpga prototype chip in which the programmable body bias voltage can be individually applied to elemental circuits such as MUXes, LUT and DFF is fabricated using low-power 90-nm bulk CMOS technology and the area overhead, dynamic current, static current and operational speed are evaluated in silicon. In measurements, 10 ISCAS benchmark circuits are implemented by employing newly developed CAD tools which consist of VT mapper as well as placer and router. Mask layout shows that well-separated margins, programmable body bias circuits, and additional configuration memories occupy 54% of the fpga tile area. Measurement results show that the fabricated fpga reduces the static current by 91.4% in average. In addition, evaluations by implementing ring oscillator with various body bias voltage pairs demonstrate the static current reduction from 23.1 uA to 1.0 uA by assigning low threshold voltage and high threshold voltage to MOSFETs on a critical path and the rest of the MOSFETs, respectively while maintaining the same oscillation frequency of 6.6 MHz as the frequency when all MOSFETs are assigned low threshold voltage. Moreover the fine-grain programmable body bias technique accelerates the oscillation frequency of ring oscillator implemented on fpga by aggressively applying forward body bias voltage, while assignment of HVT to MOSFETs on the non-critical path by applying the reverse body biasing effectively suppresses exponential increase of static current caused by the forward body biasing. © 2013 acm.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

Co-processing with dynamic reconfiguration on heterogeneous MPSoC: practices and design tradeoffs (abstract only) 14

Co-processing with dynamic reconfiguration on heterogeneous ...

引用

Proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Chao Wang Xi Li Xuehai Zhou Yunji Chen Koen Bertels University of Science and Technology of China Suzhou China University of Science and Technology of China Hefei China ICT Chinese Academy of Sciences Beijing China TU Delft Delft Netherlands

ISBN: (纸本)9781450326711

Reconfiguration technique has been considered as one of the most promising electronic design automation (EDA) technologies in MPSoC design paradigms. However, due to the unavoidable latency in the reconfiguration procedure, it still poses a significant challenge to efficiently analyze the trade-offs for the software/hardware execution, static reconfiguration and dynamic reconfiguration. In this paper we first present a heterogeneous MPSoC middleware to support state-of-the-art dynamic partial reconfigurable technologies. Furthermore, we evaluate the reconfiguration latency and analyze the trade-off for the dynamic partial reconfiguration *** a practical study, a heterogeneous MPSoC prototype with JPEG application has been developed on Xilinx Zynq fpga with state-of-the-art static/dynamic partial reconfigurable technologies. Experimental results on the JPEG case studies demonstrated the leverage among the software execution, hardware execution, and static/dynamic reconfiguration. For the quantitative approach, we have demonstrated the execution time for the different configuration of the hardware steps in JPEG, and the quantitative impact of the dynamic reconfiguration execution. The dynamic reconfiguration could gain the performance benefits for large scale (larger than a certain threshold) computational tasks. Furthermore, overheads and HWICAP hardware utilization have been measured *** work was supported by the NSFC grants No. 61379040, No. 61272131 and No. 61202053.

关键词： dynamic partial reconfiguration eda fpga heterogeneous mpsoc trade-offs

来源：评论

学校读者我要写书评

暂无评论

BMP: a fast B*-tree based modular placer for fpgas (abstract only) 14

BMP: a fast B*-tree based modular placer for FPGAs (abstract...

引用

Proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Fubing Mao Yi-Chung Chen Wei Zhang Hai Li Nanyang Technological University Singapore Singapore University of Pittsburgh Pittsburgh PA USA Hong Kong University of Science and Technology Hong Kong Hong Kong

ISBN: (纸本)9781450326711

With the wide application of fpgas in adaptive computing systems, there is an increasing need to support design automation for PR fpgas. However, there is a missing link between CAD tools for PR fpga and existing widely used CAD tools, such as VPR. Hence, in this work we propose a modular placer for fpgas because each PR region needs to be identified during partial reconfiguration and treated as an entity during placement and routing, which is not well supported by the current CAD tools. Our proposed tool is built on top of VPR. It takes the pre-synthesized module information from library, such as area, delay, etc, and performs modular placement to minimize total area and delay of the application. Modular information is represented in B*-Tree structure to allow fast placement. We amend the operations of B*-Tree to fit hardware characteristic of fpgas. Different width-height ratios of the modules are exploited to achieve area-delay product optimization. Experimental results show comparisons of area, delay and execution time with original VPR. Though it may have disadvantage in area because of blank area among modules, it improves the delay of most of benchmarks comparing to results from VPR. At the end, we show PR-aware routing based on the modular placement.

关键词： fpga cad partial reconfiguration b*-tree

来源：评论

学校读者我要写书评

暂无评论

Redefining the role of fpgas in the next generation avionic systems (abstract only) 14

Redefining the role of FPGAs in the next generation avionic ...

引用

Proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Venkatasubramanian Viswanathan Rabie Ben Atitallah Jean-Luc Dekeyser Benjamin Nakache Maurice Nakache Nolam Embedded Systems Paris France University of Valenciennes France Valenciennes France University of Lille1 France Lille France

ISBN: (纸本)9781450326711

Embedded reconfigurable computing is becoming a new paradigm for system designers in avionic applications. In fact, fpgas can be used for more than just computational purpose in order to improve the system performance. The introduction of fpga Mezzanine Card (FMC) I/O standard has given a new purpose for fpgas to be used as a communication platform. Taking into account the features offered by fpgas and FMCs, such as runtime reconfiguration and modularity, we have redefined the role of these devices to be used as a generic communication and computation-centric platform. A new modular, runtime reconfigurable, Intellectual Property (IP)-based communication-centric platform for avionic applications has been designed. This means that, when the communication requirement of an avionic system changes, the necessary communication protocol is installed and executed on demand, without disturbing the normal operation of a time-critical avionic system. The efficiency and the performances of our platform are illustrated through a real industrial use-case designed using a computationally intensive application and several avionic I/O bus standards. The reconfiguration latency can be hidden totally in many cases. While in certain others, the overhead of reconfiguration can be justified by the reduction in the resource utilization.

关键词： dynamic partial reconfiguration intensive signal processing applications avionic ip cores fpga mezzanine module modular and reconfigurable i/os

来源：评论

学校读者我要写书评

暂无评论

Heracles: A tool for fast RTL-based design space exploration of multicore processors 13

Heracles: A tool for fast RTL-based design space exploration...

引用

2013 acm/sigda international symposium on field programmable gate arrays, fpga 2013

作者： Kinsy, Michel A. Pellauer, Michael Devadas, Srinivas Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge MA United States Intel Corporation VSSAD Group Hudson MA United States

ISBN: (纸本)9781450318877

This paper presents Heracles, an open-source, functional, parameterized, synthesizable multicore system toolkit. Such a multi/many-core design platform is a powerful and versatile research and teaching tool for architectural exploration and hardware-software co-design. The Heracles toolkit comprises the soft hardware (HDL) modules, application compiler, and graphical user interface. It is designed with a high degree of modularity to support fast exploration of future multicore processors of different topologies, routing schemes, processing elements (cores), and memory system organizations. It is a component-based framework with parameterized interfaces and strong emphasis on module reusability. The compiler toolchain is used to map C or C++ based applications onto the processing units. The GUI allows the user to quickly configure and launch a system instance for easy factorial development and evaluation. Hardware modules are implemented in synthesizable Verilog and are fpga platform independent. The Heracles tool is freely available under the open-source MIT license at: http://***/heracles. © 2013 acm.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共138页 << < 57 58 59 60 61 62 63 64 65 66 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：