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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是621-630 订阅

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Power estimation tool for system on programmable chip based platforms (abstract only) 14

Power estimation tool for system on programmable chip based ...

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Proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Santhosh Kumar Rethinagiri Oscar Palomar Adrian Cristal Osman Unsal BSC - Microsoft Research Center Barcelona Spain BSC - Mircrosoft Research Center Barcelona Spain

ISBN: (纸本)9781450326711

The ever increasing complexity of the applications result in the development of power hungry processors. There is a scarcity of standalone tools that have a good trade off between estimation speed and accuracy to estimate power/energy at an earlier phase of design flow. There are very few tools that addresses the design space exploration issue based on power and energy. In this paper, we propose a virtual platform based standalone power and energy estimation tool for System-on-programmable Chip (SoPC) embedded platforms, which is independent of in-house tools. There are two steps involved in this tool development. The first step is power model generation. For the power model development, we used functional parameters to set up generic power models for the different parts of the system. This is a onetime activity. In the second step, a simulation based virtual platform framework is developed to evaluate accurately the activities used in the related power models developed in the first step. The combination of the two steps lead to a hybrid power estimation, which gives a better trade-off between accuracy and speed. The proposed tool has several benefits: it considers the power consumption of the embedded system in its entirety and leads to accurate estimates without a costly and complex material. The proposed tool is also scalable for exploring complex embedded multi-core *** effectiveness of our proposed tool is validated through dualcore RISC processor designed around the fpga board and extended to accommodate futuristic multi-core processors for a reliable energy based design space exploration. The accuracy of our proposed tool is evaluated by using a variety of industrial benchmarks such as Multimedia, EEMBC and SPEC2006. Estimated power values are compared to real board measurements and also to McPAT. Our obtained power/energy estimation results provide less than 9% of error for heterogeneous MPSoC based system and are 200% faster compared to other

关键词： power/energy estimation fpga systemc heterogeneous architecture asic tlm speedup multicore functional power models design space exploration virtual platform accuracy

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C-to-CoRAM: Compiling perfect loop nests to the portable CoRAM abstraction 13

C-to-CoRAM: Compiling perfect loop nests to the portable CoR...

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2013 acm/sigda international symposium on field programmable gate arrays, fpga 2013

作者： Weisz, Gabriel Hoe, James C. Computer Science Department Carnegie Mellon University Pittsburgh PA United States Electrical and Computer Engineering Department Carnegie Mellon University Pittsburgh PA United States

ISBN: (纸本)9781450318877

This paper presents initial work on developing a C compiler for the CoRAM fpga computing abstraction. The presented effort focuses on compiling fixed-bound perfect loop nests that operate on large data sets in external DRAM. As required by the CoRAM abstraction, the compiler partitions source code into two separate implementation components: (1) hardware kernel pipelines to be mapped onto the reconfigurable logic fabric;and (2) control threads that express, in a C-like language, the sequencing and coordination of data transfers between the hardware kernels and external DRAM. The compiler performs optimizations to increase parallelism and use DRAM bandwidth efficiently. It can target different fpga platforms that support the CoRAM abstraction, either natively in a future fpga or in soft-logic on today's devices. The CoRAM abstraction provides a convenient high-level compilation target to simplify the task of design optimization and system generation. The compiler is evaluated using three test programs (matrix-matrix multiplication, k-nearest neighbor, and 2D convolution) on the Xilinx ML605 and the Altera DE4. Results show that our compiler is able to target the different platforms and effectively exploit their dissimilar capacities and features. Depending on the application, the compiler-generated implementations achieve performance ranging from a factor of 4 slower to a factor of 2 faster relative to hand-designed implementations, as measured on actual hardware. © 2013 acm.

关键词： field programmable gate arrays (fpga)

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Design, implementation and security analysis of hardware trojan threats in fpga (abstract only) 14

Design, implementation and security analysis of hardware tro...

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Proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Devu Manikantan Shila Vivek Venugopal United Technologies Research Center E. Hartford CT USA

ISBN: (纸本)9781450326711

Hardware Trojan Threats (HTTs) are stealthy components embedded inside integrated circuits (ICs) with an intention to attack and cripple the IC similar to viruses infecting the human body. HTTs are easily introduced into the IC using untrusted tools and unauthenticated intellectual property (IP). Previous efforts have focused essentially on systems being compromised using HTTs and the effectiveness of physical parameters including power consumption, timing variation and utilization for detecting HTTs. Less attention has been devoted to the monitoring of the system to analyze the HTT infection using a combination of affected physical parameters. We propose a novel metric for hardware Trojan detection, termed as HTT detectability metric (HDM) that leverages a weighted combination of normalized physical parameters. As opposed to existing studies, this work investigates a system model from a designer perspective in increasing the security of the device and an adversary model from an attacker perspective exposing and exploiting the vulnerabilities in the device. Based on the models, seven malicious HTTs were designed and implemented on a fpga testbed to perform a variety of threats ranging from sensitive information leak, denial of service to beat the Root of Trust (RoT). Security analysis on the implemented Trojans clearly showed that existing detection techniques based on physical characteristics such as power consumption, timing variation or utilization does not necessarily capture the existence of HTTs as HTTs can be optimally designed and placed into the hardware that masks within these parameters. Our results showed that using HDM, 86% of the implemented Trojans were detected as opposed to using power, timing and utilization alone.

关键词： trojan detection design hardware trojan threats resiliency root of trust security

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High throughput and programmable online trafficclassifier on fpga 13

High throughput and programmable online trafficclassifier on...

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2013 acm/sigda international symposium on field programmable gate arrays, fpga 2013

作者： Tong, Da Sun, Lu Matam, Kiran Prasanna, Viktor Ming Hsieh Department of Electrical Engineering University of Southern California Los Angeles CA United States

ISBN: (纸本)9781450318877

Machine learning (ML) algorithms have been shown to be effective in classifying the dynamic internet traffic today. Using additional features and sophisticated ML techniques can improve accuracy and can classify a broad range of application classes. Realizing such classifiers to meet high data rates is challenging. In this paper, we propose two architectures to realize complete online traffic classifier using flow-level features. First, we develop a traffic classifier based on C4.5 decision tree algorithm and Entropy-MDL discretization algorithm. It achieves an accuracy of 97.92% when classifying a traffic trace consisting of eight application classes. Next, we accelerate our classifier using two architectures on fpga. One architecture stores the classifier in on-chip distributed RAM. It is designed to sustain a high throughput. The other architecture stores the classifier in block RAM. It is designed to operate with small hardware footprint and thus built at low hardware cost. Experimental results show that our high throughput architecture can sustain a throughput of 550 Gbps assuming 40 Byte packet size. Our low cost architecture demonstrates a 22% better resource efficiency than the high throughput design. It can be easily replicated to achieve 449 Gbps while supporting 160 input traffic streams concurrently. Both architectures are parameterizable and programmable to support any binary-tree-based traffic classifier. We develop a tool which allows users to easily map a binary-tree-based classifier to hardware. The tool takes a classifier as input and automatically generates the Verilog code for the corresponding hardware architecture. © 2013 acm.

关键词： field programmable gate arrays (fpga)

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acm/sigda international symposium on field programmable gate arrays - fpga: Foreword

ACM/SIGDA International Symposium on Field Programmable Gate...

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acm/sigda international symposium on field programmable gate arrays - fpga 2011年 iii页

作者： Wawrzynek, John Compton, Katherine UC Berkeley United States University of Wisconsin-Madison United States

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GROK-LAB: Generating real on-chip knowledge for intra-cluster delays using timing extraction 13

GROK-LAB: Generating real on-chip knowledge for intra-cluste...

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2013 acm/sigda international symposium on field programmable gate arrays, fpga 2013

作者： Gojman, Benjamin Nalmela, Sirisha Mehta, Nikil Howarth, Nicholas DeHon, André Department of Computer and Information Systems University of Pennsylvania 3330 Walnut Street Philadelphia PA 19104 United States Juniper Networks 10 Technology Park Drive Westford MA 01886 United States Department of Computer Science California Institute of Technology MC 305-16 1200 E. California Blvd. Pasadena CA 91125 United States Department of Electrical and Systems Engineering University of Pennsylvania 200 S. 33rd St. Philadelphia PA 19104 United States

ISBN: (纸本)9781450318877

Timing Extraction identifies the delay of fine-grained components within an fpga. From these computed delays, the delay of any path can be calculated. Moreover, a comparison of the fine-grained delays allows a detailed understanding of the amount and type of process variation that exists in the fpga. To obtain these delays, Timing Extraction measures, using only resources already available in the fpga, the delay of a small subset of the total paths in the fpga. We apply Timing Extraction to the Logic Array Block (LAB) on an Altera Cyclone III fpga to obtain a view of the delay down to near individual LUT granularity, characterizing components with delays on the order of a few hundred picoseconds with a resolution of ±3.2 ps. This information reveals that the 65 nm process used has, on average, random variation of σ/μ = 4.0% with components having an average maximum spread of 83 ps. Timing extraction also shows that as VDD decreases from 1.2 V to 0.9 V in a Cyclone IV 60 nm fpga, paths slow down and variation increases from σ/μ = 4.3% to σ/μ = 5.8%, a clear indication that lowering VDD magnifies the impact of random variation. © 2013 acm.

关键词： field programmable gate arrays (fpga)

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A scalable routability-driven analytical placer with global router integration for fpgas (abstract only) 14

A scalable routability-driven analytical placer with global ...

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Proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Ka Chun Lam Wai-Chung Tang Evangeline F.Y. Young The Chinese University of Hong Kong Hong Kong Hong Kong Queen Mary University of London London England UK

ISBN: (纸本)9781450326711

As the sizes of modern circuits become bigger and bigger, implementing those large circuits into fpga becomes arduous. The state-of-the-art academic fpga place-and-route tool, VPR, has good quality but needs around a whole day to complete a placement when the input circuit contains millions of lookup tables, excluding the runtime for routing. To expedite the placement process, we propose a routability-driven placement algorithm for fpga that adopts techniques used in ASIC global placer. Our placer follows the lower-bound-and-upper-bound iterative optimization process in ASIC placers like Ripple. In the lower-bound computation, the total HPWL, modeled using the Bound2Bound net model, is minimized using the conjugate gradient method. In the upper-bound computation, an almost-legalized result is produced by spreading cells linearly in the placement area. Those positions are then served as fixed-point anchors and fed into the next lower-bound computation. Furthermore, global routing will be performed in the upper-bound computation to estimate the routing segment usage, as a mean to consider congestion in placement. We tested our approach using 20 MCNC benchmarks and 4 large benchmarks for performance and scalability. Experimental results show that based on the island-style architecture which VPR is most optimized for, our approach can obtain a placement result 8x faster than VPR with 2% more in channel width, or 3x faster with 1% more in channel width when congestion is being considered. Our approach is even 14x faster than VPR in placing large benchmarks with over 10,000 lookup tables, with only 7% more in channel width.

关键词： placement fpga routability-driven

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An fpga based parallel architecture for music melody matching 13

An FPGA based parallel architecture for music melody matchin...

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2013 acm/sigda international symposium on field programmable gate arrays, fpga 2013

作者： Wang, Hao Liu, Jyh-Charn Department of Computer Science and Engineering Texas A and M University College Station TX 77840 United States

ISBN: (纸本)9781450318877

We propose an fpga-based high performance parallel architecture for music retrieval through singing. The database consists of monophonic MIDI files which are modeled into strings, and the user sung query is modeled as a set of regular expressions (regexp), with consideration of possible key transpositions and tempo variations to tolerate imperfectly sung queries. An approximate regexp matching algorithm is developed to calculate the similarity between a regexp and a string, using edit distance as the metrics. The algorithm supports user sung queries starting anywhere in the database song, not necessarily from the beginning. Using the proposed formal models and algorithms, the similarity between the user sung query and each song in the database can be evaluated and the top-10 most similar results will be reported. We designed the approximate regexp matching algorithm in such way that all terms of the regexp can execute concurrently, which perfectly fits the massive parallelism provided by fpga. The fpga implemented melody matching engine (MME) is a parameterized modular architecture that can be reconfigured to implement different regexps by simply updating their parameter registers, and can therefore avoid the time-consuming code re-synthesis. MME also includes an on-board DDR2 memory to store the database, so that they can be read in to calculate edit distances locally on the board. This way, each MME forms a self-contained system and multiple MMEs can be clustered to increase parallel processing power, with virtually no overhead. MME is evaluated using the query corpus of ThinkIT with 355 sung files and database of 5563 MIDI files. It achieves a top-10 hit rate of 90.7% and a runtime of 19.4 seconds, averaging 54.6 milliseconds for a single query. MME achieves significant speedup over software-based systems while providing the same level of flexibility. © 2013 acm.

关键词： field programmable gate arrays (fpga)

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Big data genome sequencing on Zynq based clusters (abstract only) 14

Big data genome sequencing on Zynq based clusters (abstract ...

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Proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Chao Wang Xi Li Xuehai Zhou Yunji Chen Ray C.C. Cheung University of Science and Technology of China Suzhou China University of Science and Technology of China Hefei China ICT Chinese Academy of Sciences Beijing China City University of Hong Kong Hong Kong China

ISBN: (纸本)9781450326711

Next-generation sequencing (NGS) problems have attracted many attentions of researchers in biological and medical computing domains. The current state-of-the-art NGS computing machines are dramatically lowering the cost and increasing the throughput of DNA sequencing. In this paper, we propose a practical study that uses Xilinx Zynq board to summarize acceleration engines using fpga accelerators and ARM processors for the state-of-the-art short read mapping approaches. The heterogeneous processors and accelerators are coupled with each other using a general Hadoop distributed processing framework. First the reads are collected by the central server, and then distributed to multiple accelerators on the Zynq for hardware acceleration. Therefore, the combination of hardware acceleration and Map-Reduce execution flow could greatly accelerate the task of aligning short length reads to a known reference genome. Our approach is based on preprocessing the reference genomes and iterative jobs for aligning the continuous incoming reads. The hardware acceleration is based on the creditable read-mapping algorithm RMAP software approach. Furthermore, the speedup analysis on a Hadoop cluster, which concludes 8 development boards, is evaluated. Experimental results demonstrate that our proposed architecture and methods has the speedup of more than 112X, and is scalable with the number of accelerators. Finally, the Zynq based cluster has efficient potential to accelerate even general large scale big data *** work was supported by the NSFC grants No. 61379040, No. 61272131 and No. 61202053.

关键词： genome sequencing rmap bioinformatics fpga hardware acceleration.

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An fpga memcached appliance 13

An FPGA memcached appliance

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2013 acm/sigda international symposium on field programmable gate arrays, fpga 2013

作者： Chalamalasetti, Sai Rahul Lim, Kevin Wright, Mitch AuYoung, Alvin Ranganathan, Parthasarathy Margala, Martin University of Massachusetts Lowell 1 University Avenue Lowell MA United States Hewlett Packard 1501 Page Mill Road Palo Alto CA United States Hewlett Packard Labs. 11445 Compaq Center West Drive Houston TX United States

ISBN: (纸本)9781450318877

Providing low-latency access to large amounts of data is one of the foremost requirements for many web services. To address these needs, systems such as Memcached have been created which provide a distributed, all in-memory key-value store. These systems are critical and often deployed across hundreds or thousands of servers. However, these systems are not well matched for commodity servers, as they require significant CPU resources to achieve reasonable network bandwidth, yet the core Memcached functions do not benefit from the high performance of standard server CPUs. In this paper, we demonstrate the design of an fpga-based Memcached appliance. We take Memcached, a complex software system, and implement its core functionality on an fpga. By leveraging the fpga's design and utilizing its customizable logic to create a specialized appliance we are able to tightly integrate networking, compute, and memory. This integration allows us to overcome many of the bottlenecks found in standard servers. Our design provides performance on-par with baseline servers, but consumes only 9% of the power of the baseline. Scaled out, we see benefits at the data center level, substantially improving the performance-per-dollar while improving energy efficiency by 3.2X to 10.9X. © 2013 acm.

关键词： Energy efficiency

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