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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是651-660 订阅

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A memory-efficient hardware architecture for real-time feature detection of the SIFT algorithm (abstract only) 13

A memory-efficient hardware architecture for real-time featu...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Wenjuan Deng Yiqun Zhu Department of Electrical and Electronic Engineering University of Nottingham Nottingham United Kingdom

ISBN: (纸本)9781450318877

The SIFT (Scale Invariant Feature Transform) is a most popular image processing algorithm that has been widely used in solving image matching related problems. However, SIFT is of high computational complexity and large memory requirement that prevent it from being applied to applications that are unable to offer large on-chip memory. Based on the analysis of the memory requirement of SIFT feature detection, a novel memory access strategy is proposed to reduce the hardware memory usage. In addition, to achieve real-time performance of high resolution video streams, dedicated hardware architecture with multi-pixel based processing scheme has been developed. Compared with conventional designs, our design achieves hardware memory reduction of at least 58.8%.

关键词： feature detection memory reduction sift fpga hardware architecture

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Scalable high-throughput architecture for large balanced tree structures on fpga (abstract only) 13

Scalable high-throughput architecture for large balanced tre...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Yun Qu Viktor Prasanna University of Southern California Los Angeles CA USA

ISBN: (纸本)9781450318877

Architectures for tree structures on fpgas as well as ASICs have been proposed over the years. The exponential growth in the memory size with respect to the tree levels restricts the scalability of these architectures due to limited on-chip memory. For large trees, off-chip memory has to be used. We propose a pipeline architecture on fpga for large balanced tree structures which achieves both scalability and high throughput. In the proposed architecture, each tree level is mapped onto a single or multiple Processing Elements (PEs) using dual-port distributed RAM, dual-port block RAM and off-chip RAM. We parameterize the pipeline architecture and optimize the performance with respect to scalability and throughput. The resulting architecture for the search tree is dual-threaded and deeply pipelined. It can accept two search requests per clock cycle and operates at a high clock rate of 280MHz. Post place-and-route results show that, by using only 17% of the logic resources and 9% of the BRAM available on a state-of-the-art fpga, our dual-thread pipelined search tree can perform 560 million search operations per second in a tree containing 512K 64-bit keys.

关键词： high-throughput fpga scalable tree

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High performance architecture for object detection in streamed video (abstract only) 13

High performance architecture for object detection in stream...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Pavel Zemčík Roman Juránek Petr Musil Martin Musil Michal Hradiš Brno University of Technology Brno Czech Rep

ISBN: (纸本)9781450318877

Object detection is one of the key tasks in computer vision. It is computationally intensive and it is reasonable to accelerate it in hardware. The possible benefits of the acceleration are reduction of the computational load of the host computer system, increase of the overall performance of the applications, and reduction of the power consumption. We present novel architecture for multi-scale object detection in video streams. The architecture uses scanning window classifiers produced by WaldBoost learning algorithm, and simple image features. It employs small image buffer for data under processing, and on-the-fly scaling units to enable detection of object in multiple scales. The whole processing chain is pipelined and thus more image windows are processed in parallel. We implemented the engine in Spartan 6 fpga and we show that it can process 640x480 pixel video streams at over 160 frames per second without the need of external memory. The design takes only a fraction of resources, compared to similar state of the art approaches.

关键词： fpga object detection local binary patterns waldboost stream processing local rank functions

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A latency-optimized hybrid network for clustering fpgas (abstract only) 13

A latency-optimized hybrid network for clustering FPGAs (abs...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Trevor Bunker Steven Swanson University of California San Diego La Jolla CA USA

ISBN: (纸本)9781450318877

The data-intensive applications that will shape computing in the coming decades require scalable architectures that incorporate scalable data and compute resources and can support unstructured (e.g., logs) and semi-structured (e.g., large graph, XML) data sets. To explore the suitability of fpgas for these computations, we are constructing an fpga-based system with a memory capacity of 512 GB from a collection of 32 Virtex-5 fpgas spread across 8 enclosures. This poster describes the system's interconnect that combines inter-enclosure high-speed serial links and wide, single-ended intra-enclosure on-board traces with a network topology that optimizes for latency and bandwidth for small packets. The network uses a multi-level radix-12 router optimized for the asymmetry between the inter- and intra-enclosure links. The system has a peak theoretical bisection bandwidth of 247.2 Gb/s and a total switching capacity of 2.13 Tb/s. Under random traffic, the network sustains an aggregate throughput of 354.3 Gb/s. The channel transceivers and router consume 22% of the fpgas' Block RAMs and 33% of their fpga Slices.

关键词： data-intensive applications high-speed serial high-radix router fpga low latency network

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Low power fpga design using post-silicon device aging (abstract only) 13

Low power FPGA design using post-silicon device aging (abstr...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Sheng Wei Jason Xin Zheng Miodrag Potkonjak University of California Los Angeles Los Angeles CA USA

ISBN: (纸本)9781450318877

The impact of process variation (PV) in deep submicron CMOS technologies has raised major concerns for energy optimization efforts in fpgas. We have developed a post-silicon leakage energy optimization scheme that raises the threshold voltage (by way of negative bias temperature instability (NBTI) aging) of the components that are either unused or not on the critical timing paths, thereby reducing the total leakage energy consumption. In order to obtain the input vectors for aging only the targeted transistors, we map the problem of minimizing leakage energy under timing constraints to an instance of the satisfiability (SAT) problem. We implemented low power designs targeting Xilinx Spartan6 fpgas and analyzed the potential leakage power savings over a set of ITC99 and Opencores benchmarks. The analysis of the experimental results shows a substantial amount of potential leakage energy reduction with very small performance degradation.

关键词： low power process variation negative bias temperature instability

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Genome sequencing using mapreduce on fpga with multiple hardware accelerators (abstract only) 13

Genome sequencing using mapreduce on FPGA with multiple hard...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Chao Wang Xi Li Xuehai Zhou Jim Martin Ray C.C. Cheung University of Science and Technology of China Suzhou China University of Science and Technology of China Hefei China Clemson University Clemson SC USA City University of Hong Kong Hong Kong Hong Kong

ISBN: (纸本)9781450318877

The genome sequencing problem with short reads is an emerging field with seemingly limitless possibilities for advances in numerous scientific research and application domains. It has been the hot topic during the past few years. Growing with the data population and the ease to access for personal users, how to shorten the response interval for short read mapping at a large scale computing domain is extremely important. In this paper we propose a novel fpga-based acceleration solution with Map-Reduce framework on multiple hardware acceleration engines. The combination of hardware accelerators and Map-Reduce execution flow could greatly expedite the task of aligning short length reads to a known reference genome. Our approach is based on preprocessing the reference genomes and iterative jobs for aligning the continuous incoming reads. The read-mapping algorithm is modeled after the creditable RMAP software approach. Furthermore, theoretical speedup analysis on a MapReduce programming platform is presented, which demonstrates that our proposed architecture has efficient potential to reduce the average waiting time for large scale short reads applications.

关键词： short reads fpga genome sequencing mapreduce

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An fpga-based transient error simulator for evaluating resilient system designs (abstract only) 13

An FPGA-based transient error simulator for evaluating resil...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Chia-Hsiang Chen Shiming Song Zhengya Zhang University of Michigan Ann Arbor MI USA

ISBN: (纸本)9781450318877

Error-resilient designs have become more important with the continued device scaling. One critical challenge of designing error-resilient systems is the lack of tools to quickly and accurately evaluate the effectiveness and performance of such systems. We propose an fpga-based transient error simulator to accelerate transient error simulations incorporating accurate datapath delay models and realistic error models. Compared to conventional digital error simulators, the fpga-based transient error simulator operates at a finer time step and captures intricate interactions between errors and datapath under different circuit-level error detection and correction techniques. The error simulator is constructed using configurable datapath delay model and error model, making it general-purpose and widely applicable. We demonstrate the capability of this simulator in the evaluation of two popular error-resilient design techniques, pre-edge and post-edge detection and correction, using a synthesized CORDIC processor and an Alpha processor that operate under soft error, coupling noise and voltage droop models. The proposed error simulator uncovers insights to guide practical designs, including the choice of checking window in pre-edge designs and the optimal operating frequency in post-edge designs. The fpga-based transient simulation will complement circuit simulation and system emulation for resilient system designs.

关键词： transient simulation reliability error detection and correction error-resilient design fpga-based simulation

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VirtualRC: A Virtual fpga Platform for Applications and Tools Portability 12

VirtualRC: A Virtual FPGA Platform for Applications and Tool...

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20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Kirchgessner, Robert Stitt, Greg George, Alan Lam, Herman Univ Florida Dept Elect & Comp Engn NSF Ctr High Performance Reconfigurable Comp CHREC Gainesville FL 32611 USA

ISBN: (纸本)9781450311557

Numerous studies have shown significant performance and power benefits of field-programmable gate arrays (fpgas). Despite these benefits, fpga usage has been limited by application design complexity caused largely by the lack of code and tool portability across different fpga platforms, which prevents design reuse. This paper addresses the portability challenge by introducing a framework of architecture and middleware for virtualization of fpga platforms, collectively named VirtualRC. Experiments show modest overhead of 5-6% in performance and 1% in area, while enabling portability of 11 applications and two high-level synthesis tools across three physical platforms.

关键词： fpga portability virtual architectures

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Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only) 13

Shadow AICs: reaping the benefits of and-inverter cones with...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Hadi Parandeh-Afshar Grace Zgheib David Novo Madhura Purnaprajna Paolo Ienne Ecole Polytechnique Fédérale de Lausanne (EPFL) Lausanne Switzerland

ISBN: (纸本)9781450318877

Despite their many advantages, fpgas are still inefficient. This inefficiency is mainly due to programmable routing networks; however, fpga logic blocks also have their share of contribution. From the performance perspective, fewer hops in the routing network translates to a shorter critical path; and that requires large logic blocks capable of covering big portions of circuits. Recent work has shown that And-Inverter Cones (AICs) can considerably reduce the number of logic block levels compared to Look-Up Tables (LUTs). The best performance is achieved when both AICs and LUTs are used, but the AIC implementation requires radical changes in the fpgas architecture. In this paper, we use AICs as shadow logic for LUTs in LUT-clusters, which requires minimal architectural changes while exploiting the benefits of both AICs and LUTs. The basic idea is to reuse the input crossbar of LUT-clusters for the shadow AICs while combining both LUTs and AICs in the same cluster. We also propose changes in the AIC architecture to enhance mapping on AICs. Our experimental results indicate that the new cluster architecture can reduce the average circuit delay by 12% with respect to standard fpga clusters. However, this performance gain comes at a price of 43% area overhead in terms of number of logic clusters. Our results show that for a modest 6% increase in area, fpga manufacturers can move towards next-generation fpga logic elements. This transition would provide faster design options without major architectural changes.

关键词： fpga logic block and-inverter cone shadow logic technology mapping

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Performance and toolchain of a combined GPU/fpga desktop (abstract only) 13

Performance and toolchain of a combined GPU/FPGA desktop (ab...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Bruno da Silva An Braeken Erik H. D'Hollander Abdellah Touhafi Jan G. Cornelis Jan Lemeire Erasmus University College Brussels Belgium Ghent University Ghent Belgium Free University of Brussels Brussels Belgium

ISBN: (纸本)9781450318877

Low-power, high-performance computing nowadays relies on accelerator cards to speed up the calculations. Combining the power of GPUs with the flexibility of fpgas enlarges the scope of problems that can be accelerated [2, 3]. We describe the performance analysis of a desktop equipped with a GPU Tesla 2050 and an fpga Virtex-6 LX240T. First, the balance between the I/O and the raw peak performance is depicted using the roofline model [4]. Next, the performance of a number of image processing algorithms is measured and the results are mapped onto the roofline graph. This allows to compare the GPU and the fpga and also to optimize the algorithms for both accelerators. A programming toolchain is implemented, consisting of OpenCL for the GPU and several High-Level Synthesis compilers for the fpga. Our results show that the HLS compilers outperform handwritten code and offer a performance comparable to the GPU. In addition the fpga compilers reduce the development time by an order of magnitude, at the expense of an increased resource consumption. The roofline model also shows that both accelerators are equally limited by the input/output bandwidth to the host. A well-tuned accelerator-based codesign, identifying the parallelism, the computation and data patterns of different classes of algorithms, will enable to maximize the performance of the combined GPU/fpga system [1].

关键词： HLS compilers performance opencl programming toolchain fpga accelerators GPU

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