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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是661-670 订阅

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A Lean fpga Soft Processor Built Using a DSP Block 12

A Lean FPGA Soft Processor Built Using a DSP Block

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20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Cheah, Hui Yan Fahmy, Suhaib A. Maskell, Douglas L. Kulkarni, Chidamber Nanyang Technol Univ Sch Comp Engn Singapore Singapore

ISBN: (纸本)9781450311557

As field programmable gate arrays (fpgas) have advanced, the capabilities and variety of embedded resources have increased. In the last decade, signal processing has become one of the main driving applications for fpga adoption, so fpga vendors tailored their architectures to such applications. The resulting embedded digital signal processing (DSP) blocks have now advanced to the point of supporting a wide range of operations. In this paper, we explore how these DSP blocks can be applied to general computation. We show that the DSP48E1 blocks in Xilinx Virtex-6 devices support a wide range of standard processor instructions which can be designed into the core of a basic processor with minimal additional logic usage.

关键词： fpga DSP blocks soft processor hard macro

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AutoMapper: an automated tool for optimal hardware resource allocation for networking applications on fpga (abstract only) 13

AutoMapper: an automated tool for optimal hardware resource ...

引用

Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Swapnil D. Haria Viktor Prasanna Birla Institute of Technology & Science Pilani India University of Southern California Los Angeles CA USA

ISBN: (纸本)9781450318877

It has now become imperative for routers to support complicated lookup schemes, based on the specific function of the networking hardware. It is no longer possible to ensure an optimal resource utilization using manual organization techniques due to the increasing complexity of lookup schemes, as well as the large number of potential implementation choices. We have developed an automated tool, AutoMapper, which can map lookup schemes onto a particular target architecture optimally, thereby providing a superior alternative to the time-consuming and resource inefficient technique of manual conversion. It is based on an Integer Linear Programming (ILP) formulation that is able to allocate the limited hardware resources for a single lookup scheme, while optimizing any of the three performance metrics of latency, throughput or power consumption. Accurate formulation of the objective function and the constraint equations guarantee optimality in terms of the chosen performance metric. We demonstrate the operation of the developed tool, by successfully mapping complex real world lookup schemes onto a state-of-the art fpga device, with execution times being under a second on a dual-core computer with 4 GB of RAM, running at 2.40 GHz.

关键词： high-level tool resource allocation networking

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fpga-based acceleration of cascaded support vector machines for embedded applications (abstract only) 13

FPGA-based acceleration of cascaded support vector machines ...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Christos Kyrkou Christos Savvas Bouganis Theocharis Theocharides University of Cyprus & KIOS Research Center Nicosia Cyprus London Imperial College London United Kingdom

ISBN: (纸本)9781450318877

Support Vector Machines (SVMs) are considered one of the most popular classification algorithms yielding high accuracy rates. However, SVMs often require processing a large number of support vectors, making the classification process computationally demanding, and hence it is challenging to meet real-time processing constraints imposed by many embedded applications. In order to improve SVM classification times the cascade classification scheme has been proposed. However, even in this case real-time performance is still challenging to achieve without exploiting the throughput and processing requirements of each cascade stage. Hence the design of an fpga-based accelerator for cascaded SVM processing is proposed; in addition to a hardware reduction method in order to reduce the implementation requirements of the cascade SVM leading to significant resource savings. The accelerator was implemented on a Virtex 5 fpga platform and evaluated using face detection as the target application on 640×480 resolution images. It was compared against fpga implementations of the same cascade processing architecture but without using the reduction method, and a single parallel SVM classifier. The accelerator is capable an average performance of 70 frames-per-second, achieving a speed-up of 5× over the single parallel SVM classifier. Furthermore, the hardware reduction method results in the utilization of 43% less fpga LUT resources, with only 0.7% reduction in classification accuracy.

关键词： parallel architecture support vector machines hardware adaptation fpga cascaded classifiers

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Cross-platform fpga accelerator development using CoRAM and CONNECT 13

Cross-platform FPGA accelerator development using CoRAM and ...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Eric S. Chung Michael K. Papamichael Gabriel Weisz James C. Hoe Microsoft Research Mountain View CA USA Carnegie Mellon Pittsburgh PA USA

ISBN: (纸本)9781450318877

The CoRAM memory architecture is an easy-to-use and portable abstraction for fpga accelerator development [1, 2]. Using the CoRAM framework, fpga developers can write their applications once and re-target them automatically to different fpga platforms and devices (e.g., Xilinx ML605, Altera DE4, ZYNQ-702, etc). In this tutorial, participants will learn the key concepts of the CoRAM Virtual Architecture and the underlying CONNECT Network-on-Chip generation framework [3]. The tutorial is organized into three parts. The first part will provide an overview of the CoRAM Virtual Architecture and include a hands-on section where participants will work on a small example to get first-hand experience with the CoRAM development flow. The second part of the tutorial will provide a beneath-the-hood look at CoRAM and cover more advanced topics. These topics include memory loading, user I/O, debugging, as well as a segment on the CONNECT NoC generation framework which serves as the on-chip interconnect for CoRAM. The final part of the tutorial will be devoted to more advanced exercises and demos, as well as a Q&A session for CoRAM and CONNECT. The tutorial assumes a basic understanding of RTL design and C programming. To join in on the hands-on exercise, the attendees need laptops with 15GB of free space and VirtualBox installed. Please visit http://***/~coram for information about CoRAM and updates on this tutorial.

关键词： network-on-chip fpga computing memory architecture

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X-ORCA: fpga-Based Wireless Localization in the Sub-Millimeter Range 12

X-ORCA: FPGA-Based Wireless Localization in the Sub-Millimet...

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20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Hinkfoth, Matthias Heinrich, Enrico Vorkoeper, Sebastian Kuehn, Volker Salomon, Ralf Univ Rostock Fac Comp Sci & Elect Engn D-18051 Rostock Germany

ISBN: (纸本)9781450311557

Recent research has developed a new, entirely digital architecture, called X-ORCA, that determines the phase shift of two periodic signals with a resolution as good as about 20 Ps. This paper incorporates the X-ORCA system into a wireless experimental setup to form a localization system. The practical experiments utilize a 2.484 GHz transmitter and run the X-ORCA core on a Cyclone II fpga. The results indicate that this simple localization system easily yields a spatial resolution in the sub-millimeter range.

关键词： localization

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A novel run-time auto-reconfigurable fpga architecture for fast fault recovery with backward compatibility (abstract only) 13

A novel run-time auto-reconfigurable FPGA architecture for f...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Hasan Baig Jeong-A Lee Chosun University Gwangju South Korea

ISBN: (纸本)9781450318877

A self-repairing fault-tolerant fpga architecture is developed which is also compatible with existing island-style routing network. Due to this backward compatibility, the proposed architecture can not only be implemented easily in the existing fpga devices but a new fault-tolerant fpga device can also be fabricated utilizing the existing island-style routing architecture. A generic fault-tolerant Computation Cell is developed which can be incorporated in existing fpga CLB (Configurable Logic Block) having 8 LUTs at least. The proposed fault-tolerant fpga architecture is comprised of Computation Tiles each of which consists of computation cells which are able to heal themselves from transient errors. Computation Tile also contains stem cells which help computation cells to recover from permanent errors all at once. This architecture is centrally controlled by an on-chip fault-tolerant core whose main responsibility is to define the healing priority when an error occurs in more than one of the computation tile at the same time. It also communicates with the external PC software which identifies the faulty tile and reconfigures it through dynamic partial reconfiguration. The robust operation of a proposed architecture is implemented and verified on XILINX Virtex-5 fpga device. From our proposed fault-tolerant scheme of utilizing the existing routing strategies together with partial reconfiguration of stem cells we achieved a number of benefits, including a fast fault recovery and avoidance of using complicated routing strategies, as compared to recently developed fault-tolerant fpga architectures.

关键词： stem cell system biology fault-tolerance self-reconfiguration partial reconfiguration self-repair fpga

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A Real-time Stereo Vision System Using a Tree-structured Dynamic Programming on fpga 12

A Real-time Stereo Vision System Using a Tree-structured Dyn...

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20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Jin, Minxi Maruyama, Tsutomu Univ Tsukuba Tsukuba Ibaraki 3058573 Japan

ISBN: (纸本)9781450311557

Many hardware systems for stereo vision have been proposed. Their processing speed is very fast, but the algorithms used in them are limited in order to achieve the high processing speed by simplifying the sequences of the memory accesses and operations. The error rates by them can not compete with those by software programs. In this paper, we describe an fpga implementation of a tree-structured dynamic programming algorithm. The computational complexity of this algorithm is higher than those by previous hardware systems, but the processing speed of our system is still fast enough for real-time applications, and its error rate is competitive with software algorithms.

关键词： fpga stereo vision real-time

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Securing Netlist-Level fpga Design through Exploiting Process Variation and Degradation 12

Securing Netlist-Level FPGA Design through Exploiting Proces...

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20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Zheng, Jason Xin Potkonjak, Miodrag Univ Calif Los Angeles Dept Comp Sci Los Angeles CA 90024 USA

ISBN: (纸本)9781450311557

The continuously widening gap between the Non-Recurring Engineering (NRE) and Recurring Engineering (RE) costs of producing Integrated Circuit (IC) products in the past few decades gives high incentives to unauthorized cloning and reverse-engineering of ICs. Existing IC Digital Rights Management (DRM) schemes often demands high overhead in area, power, and performance, or require non-volatile storage. Our goal is to develop a novel Intellectual Property (IP) protection technique that offers universal protection to both Application-Specific integrated Circuits (ASIC) and field-programmable gate-arrays (fpgas) from unauthorized manufacturing and reverse engineering. In this paper we show a proof-of-concept implementation of the basic elements of the technique, as well as a case study of applying the anti-cloning technique to a nontrivial fpga design.

关键词： IP protection active hardware metering unclonable

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Co-simulation framework of SystemC SoC virtual prototype and custom logic (abstract only) 13

Co-simulation framework of SystemC SoC virtual prototype and...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Nick Ni Yi Peng Altera Corporation San Jose CA USA

ISBN: (纸本)9781450318877

To address the increasing demand of System-on-Chip (SoC) for high performance applications and IP programmability, specialized SoC with custom logic is developed in a single chip or multi-chip system. Like any other SoC platforms, early software development before hardware availability using a Virtual Prototype (VP) is essential. However, the existing RTL for custom logic makes it non-trivial to simulate the entire system with software models written in high-level language (i.e. SystemC/C/C++). In this paper, we describe our unique virtual prototyping framework called "fpga-In-the-Loop (FIL)" to enable co-simulation of software models in the VP and custom logic running in the fpga at native speed. This platform enables designers to start early software development and integration of the entire hardware platform without needing to develop software models for custom logic. More importantly, our contributions lie in overcoming two of the biggest challenges in such co-simulation systems; 1) the communication channel performance bottleneck and 2) software-visible asynchronous signal timing correctness (i.e. interrupt). Our framework was able to 1) optimize communications between the VP and fpga to achieve up to 872 Mbps effective throughput and 2) guarantee software-visible asynchronous signal delivery timing (i.e. interrupts) between the two simulation domains. Finally, we implemented our framework on a commercial hybrid platform with SoC and fpga to demonstrate the complete embedded Linux stack communicating with custom video/touchscreen IPs running in the fpga.

关键词： embedded software co-simulation SoC virtual prototype TLM custom logic virtual platform fpga SystemC

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A Fast Discrete Placement Algorithm for fpgas 12

A Fast Discrete Placement Algorithm for FPGAs

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20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Wu, Qinghong McElvain, Kenneth S. Synopsys Inc Mountain View CA 94043 USA

ISBN: (纸本)9781450311557

Good fpga placement is crucial to obtain the best Quality of Results (QoR) from fpga hardware. Although many published global placement techniques place objects in a continuous ASIC-like environment, fpgas are discrete in nature, and a continuous algorithm cannot always achieve superior QoR by itself. Therefore, discrete fpga-specific detail placement algorithms are used to improve the global placement results. Unfortunately, most of these detail placement algorithms do not have a global view. This paper presents a discrete "middle" placer that fills the gap between the two placement steps. It works like simulated annealing, but leverages various acceleration techniques. It does not pay the runtime penalty typical of simulated annealing solutions. Experiments show that with this placer, final QoR is significantly better than with the global-detail placer approach.

关键词： Computer-aided design (CAD) individual cell temperature window masking dynamic window field-programmable gate array (fpga) placement simulated annealing

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