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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是681-690 订阅

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Reliability of a Softcore Processor in a Commercial SRAM-Based fpga 12

Reliability of a Softcore Processor in a Commercial SRAM-Bas...

引用

20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Rollins, Nathaniel H. Wirthlin, Michael J. Brigham Young Univ NSF Ctr High Performance Reconfigurable Comp CHRE Provo UT 84602 USA

ISBN: (纸本)9781450311557

Softcore processors are an attractive alternative to using radiation-hardened processors in space-based applications. Unlike traditional processors however, the logic and routing of a softcore processor are vulnerable to the effects of single-event upsets (SEUs). This paper applies two common SEU mitigation techniques, TMR with checkpointing and DWC with checkpointing, to the LEON3 softcore processor. The improvement in reliabilty over an unmitigated version of the processor is measured using three metrics: the architectural vulnerability factor (AVF), mean time to failure (MTTF), and mean useful instructions to failure (MuITF). Using configuration memory fault injection, we found that DWC with checkpointing improves the MTTF and MuITF by over 35 x, and that TMR, with triplicated input and outputs improves the MTTF and MITF by over 6000x.

关键词： Reliability Softcore processors AVF MTTF MuITF

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Accelerator Compiler for the VENICE Vector Processor 12

Accelerator Compiler for the VENICE Vector Processor

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20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Liu, Zhiduo Severance, Aaron Singh, Satnam Lemieux, Guy G. F. Univ British Columbia Dept ECE Vancouver BC Canada

ISBN: (纸本)9781450311557

This paper describes the compiler design for VENICE, a new soft vector processor (SVP). The compiler is a new back-end target for Microsoft Accelerator, a high-level data parallel library for C++ and C#. This allows us to automatically compile high-level programs into VENICE assembly code, thus avoiding the process of writing assembly code used by previous SVPs. Experimental results show the compiler can generate scalable parallel code with execution times that are comparable to hand-written VENICE assembly code. On data-parallel applications, VENICE at 100MHz on an Altera DE3 platform runs at speeds comparable to one core of a 3.5GHz Intel Xeon W3690 processor, beating it in performance on four of six benchmarks by up to 3.2x.

关键词： vector SIMD soft processors scratchpad memory fpga

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Analyzing and Predicting the Impact of CAD Algorithm Noise on fpga Speed Performance and Power 12

Analyzing and Predicting the Impact of CAD Algorithm Noise o...

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20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Shum, Warren Anderson, Jason H. Univ Toronto Dept ECE Toronto ON Canada

ISBN: (纸本)9781450311557

fpga CAD algorithms are heuristic, and generally make use of cost functions to gauge the value of one potential circuit implementation over another. At times, such algorithms must decide between two or more implementation options of apparently equal cost. This work explores the variations in circuit quality, i.e. noise, that arise when CAD algorithms are altered to choose randomly when faced with such equal-cost alternatives. Noise sources are identified in logic synthesis and technology mapping algorithms, and experimental results are presented which show standard deviations of 3.3% and 3.7% from the mean in post-routed delay and power. As a means of dealing with this variation, early timing and power prediction metrics can be applied after technology mapping to find the best circuits in the presence of noise. When applied to designs with over 1.5% variation in delay and power, the best prediction models have a 40% probability of capturing the best circuit when predicting the top 10% of circuits in a group of noise-injected circuits.

关键词： fpgas CAD noise prediction

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Rectification of advanced microprocessors without changing routing on fpgas (abstract only) 13

Rectification of advanced microprocessors without changing r...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Satoshi Jo Amir Masoud Gharehbaghi Takeshi Matsumoto Masahiro Fujita The University of Tokyo Tokyo Japan

ISBN: (纸本)9781450318877

We propose a method for rectification of bugs in microprocessors that are implemented on fpgas, by only changing the configuration of LUTs, without any modification to the routing. Therefore, correcting the bugs does not require resynthesis, which can be very long for complex microprocessors due to possible timing closure problems. As the structure of the circuit is preserved, correcting the bugs does not affect the timings of the circuit. In design phase, we may add additional LUTs to the original circuit, so that we can use them in the correction phase. After a bug is found, we perform the following two tasks. Fist, we find the candidate control signals as well as the required change to correct their behavior. This is done by using symbolic simulation and equivalency checking between the formal specification and the erroneous formal model of the processor. Then, we try to map the corrected functionality into the existing LUT structure. This is done by a novel method that formulates the problem as a QBF (Quantified Boolean Formula) problem, and solves it by repeatedly applying normal SAT solvers instead of QBF solvers under a CEGAR (Counter Example Guided Abstraction Refinement) paradigm. We show effectiveness of our method by correcting bugs in two complex out-of-order superscalar processors with two different timing error recovery mechanisms.

关键词： QBF design error diagnosis design error rectification formal verification microprocessors CEGAR fpga

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Functionally Verifying State Saving and Restoration in Dynamically Reconfigurable Systems 12

Functionally Verifying State Saving and Restoration in Dynam...

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20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Gong, Lingkan Diessel, Oliver Univ New S Wales Sch Comp Sci & Engn Sydney NSW 2052 Australia

ISBN: (纸本)9781450311557

Dynamically reconfigurable systems increase design density and flexibility by allowing hardware modules to be swapped at run time. Systems that employ checkpointing, periodic or phased execution, preemptive multitasking and resource defragmentation, may also need to be able to save and restore the state of a module that is being reconfigured. Existing tools verify the functionality of a system that is undergoing reconfiguration. These tools can also be employed if state is accessed using application logic. However, when state is accessed via the configuration port, functional verification is hindered because the fpga fabric, which mediates the transfer of state between the application logic and the configuration port, is not being simulated. We describe how to efficiently simulate those aspects of the fabric that are used in accessing module state. To the best of our knowledge, this work is the first to allow cycle-accurate simulation of a system partially reconfiguring both its logic and state and a case study shows that our method is effective in detecting device independent design errors.

关键词： fpga Dynamically Reconfigurable Systems Verification State Saving and Restoration

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A novel multithread routing method for fpgas (abstract only) 13

A novel multithread routing method for FPGAs (abstract only)

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Chun Zhu Qiuli Li Jian Wang Jinmei Lai Fudan University Shanghai China

ISBN: (纸本)9781450318877

We propose a platform-independent multithread routing method for fpgas including two aspects: single high fanout net is routed parallel within itself and several low fanout nets are routed parallel between themselves. Routing for high fanout nets usually takes considerable time because of the large physical area surrounded by bounding boxes to traverse and tens of terminals to connect. Therefore, one high fanout net is partitioned into several subnets with fewer terminals and smaller bounding boxes to be routed in parallel. However, low fanout nets with intrinsic small bounding boxes and few terminals could hardly be divided. Instead, low fanout nets whose bounding boxes are not overlapping with each other are routed concurrently. A new graph, named bounding box graph, was utilized to facilitate the process of selecting several nets to be routed concurrently. In this graph, one vertex stands for a corresponding net and one edge between two connected vertex means that the two represented nets have their bounding boxes overlapped. Several strategies are introduced to balance the load among threads and ensure the deterministic results. The routing times scale down with increasing number of threads. On a 4-core processor, this technique improves the run-time by ~1.9 × with routing quality degrading by no more than 2.3%.

关键词： fpga routing bounding box graph multithread platform-independent high fanout nets low fanout nets

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Intra-Masking Dual-Rail Memory on LUT Implementation for Tamper-Resistant AES on fpga 12

Intra-Masking Dual-Rail Memory on LUT Implementation for Tam...

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20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Hoang, Anh-Tuan Fujino, Takeshi Ritsumeikan Univ Kusatsu Shiga 5258577 Japan

ISBN: (纸本)9781450311557

In current countermeasure design trends against differential power analysis (DPA), security at gate level is required in addition to the security algorithm. Several dual-rail pre-charge logics (DPL) have been proposed to achieve this goal. Designs using ASIC can attain this goal owing to its backend design restrictions on placement and routing. However, implementing these designs on field programmable gate arrays (fpga) without information leakage is still a problem because of the difficulty involved in the restrictions on placement and routing on fpga. This paper describes our novel masked dual-rail pre-charged memory approach, called "intra-masking dual-rail memory on LUT," and its implementation on fpga for tamper-resistant AES. In the proposed design, all unsafe nodes, such as unmasking and masking, and the dual-rail memory and buses are packed into a single LUT. This makes them balanced and independent of the placement and routing tools. The design is independent of the cryptographic algorithm, and hence, it can be applied to available cryptographic standards such as DES or AES as well as future standards. It requires no special placement or route constraints in its implementation. A correlation power analysis (CPA) attack on 1,000,000 traces of AES implementation on fpga showed that the secret information is well protected against first-order side-channel attacks. Even though the number of LUTs used for memory in this implementation is seven times greater than that of the conventional unprotected single-rail memory table-lookup AES and three times greater than the implementation based on a composite field, it requires a smaller number of LUTs than all other advanced tamper-resistant implementations such as the wave dynamic differential logic, masked dual-rail pre-charge logic, and threshold.

关键词： Side-Channel Attack Differential Power Analysis (DPA) Masking Dual-Rail Memory Intra-Masking Dual-Rail Memory on LUT Tamper Resistance AES field programmable gate Array (fpga)

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Impact of fpga architecture on resource sharing in high-level synthesis 12

Impact of FPGA architecture on resource sharing in high-leve...

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2012 acm/sigda international symposium on field programmable gate arrays, fpga'12

作者： Hadjis, Stefan Canis, Andrew Anderson, Jason H. Choi, Jongsok Nam, Kevin Brown, Stephen Czajkowski, Tomasz ECE Department University of Toronto Toronto ON Canada Altera Toronto Technology Centre Toronto ON Canada

ISBN: (纸本)9781450311557

Resource sharing is a key area-reduction approach in high-level synthesis (HLS) in which a single hardware functional unit is used to implement multiple operations in the high-level circuit specification. We show that the utility of sharing depends on the underlying fpga logic element architecture and that different sharing trade-offs exist when 4-LUTs vs. 6-LUTs are used. We further show that certain multi-operator patterns occur multiple times in programs, creating additional opportunities for sharing larger composite functional units comprised of patterns of interconnected operators. A sharing cost/benefit analysis is used to inform decisions made in the binding phase of an HLS tool, whose RTL output is targeted to Altera commercial fpga families: Stratix IV (dual-output 6-LUTs) and Cyclone II (4-LUTs). © 2012 acm.

关键词： field programmable gate arrays (fpga)

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fpga'10 - Proceedings of the 18th acm sigda international symposium on field-programmable gate arrays

FPGA'10 - Proceedings of the 18th ACM SIGDA International Sy...

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18th acm sigda international symposium on field-programmable gate arrays, fpga'10

ISBN: (纸本)9781605589114

The proceedings contain 34 papers. The topics discussed include: fpga prototyping of an AMBA-based Windows-compatible SoC;predicting the performance of application-specific NoCs implemented on fpgas;energy efficient sensor node implementations;high throughput and large capacity pipelined dynamic search tree on fpga;FPMR: MapReduce framework on fpga: a case study of RankBoost acceleration;Axel: a heterogeneous cluster with fpgas and GPUs;building a faster Boolean matcher using bloom filter;scalable network virtualization using fpgas;maximizing area-constrained partial fault tolerance in reconfigurable logic;fpga based chip emulation system for test development and verification of analog and mixed signal circuits;a semi-automatic Toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning;and a dependency graph based methodology for parallelizing HLL applications on fpga.

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Speedy fpga-Based Packet Classifiers with Low On-Chip Memory Requirements 12

Speedy FPGA-Based Packet Classifiers with Low On-Chip Memory...

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20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Chou, Chih-Hsun Pong, Fong Tzeng, Nian-Feng Univ Louisiana Lafayette Ctr Adv Comp Studies Lafayette LA 70504 USA

ISBN: (纸本)9781450311557

This article pursues speedy packet classification with low on-chip memory requirements realized on Xilinx Virtext-6 fpga. Based on hashing round-down prefixes specified in filter rules (dubbed HaRP), our implemented classifier is demonstrated to exhibit an extremely low on-chip memory requirement (lowering the byte count per rule by a factor of 8.6 in comparison with its most recent counterpart [2]), taking only 50% of Virtex-6 on-chip memory to store every large rule dataset (with some 30K rules) examined. In addition, it achieves a higher throughput than any known fpga implementation, reaching more than 200 MPPS (millions packet lookups per second) with 8 processing units and 8 memory banks in the HaRP pipeline to support the line rate over 130 Gbps under bi-directional traffic in the worst case with 40-byte packets. By reducing memory probes per lookup, enhanced HaRP can further boost the classification speed to 255 MPPS.

关键词： fpgas filter datasets hash tables memory efficiency pipelined design set-associativity

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