Numerous studies have shown significant performance and power benefits of field-programmablegatearrays (fpgas). Despite these benefits, fpga usage has been limited by application design complexity caused largely by ...
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ISBN:
(纸本)9781450311557
Numerous studies have shown significant performance and power benefits of field-programmablegatearrays (fpgas). Despite these benefits, fpga usage has been limited by application design complexity caused largely by the lack of code and tool portability across different fpga platforms, which prevents design reuse. This paper addresses the portability challenge by introducing a framework of architecture and middleware for virtualization of fpga platforms, collectively named VirtualRC. Experiments show modest overhead of 5-6% in performance and 1% in area, while enabling portability of 11 applications and two high-level synthesis tools across three physical platforms.
A reconfigurable logic element (LE) is developed for use in constructing a NULL Convention Logic (NCL) fpga. It can be configured as any of the 27 fundamental NCL gates, including resettable and inverting variations, ...
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ISBN:
(纸本)9781595936004
A reconfigurable logic element (LE) is developed for use in constructing a NULL Convention Logic (NCL) fpga. It can be configured as any of the 27 fundamental NCL gates, including resettable and inverting variations, and can utilize embedded registration for gates with three or fewer inputs. The developed LE is compared with a previous NCL LE, showing that the one developed herein yields a more area efficient NCL circuit implementation. The NCL fpga logic element is simulated at the transistor level using the 1.8V, 180nm TSMC CMOS process.
This paper develops a trace-bused framework to enable concurrent process and fpga architecture co-development. Based on process parameters and traces for fpga applications, the framework calculates the chip level perf...
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ISBN:
(纸本)9781595939340
This paper develops a trace-bused framework to enable concurrent process and fpga architecture co-development. Based on process parameters and traces for fpga applications, the framework calculates the chip level performance and power distribution and soft error rate (SER) with consideration of process variations and device aging. As examples to utilize the framework, the paper further applies heterogeneous gate lengths to logic and interconnects for energy reduction, and studies the interaction between device aging, process variation and SER.
This paper describes a technique that reduces dynamic power in fpgas by reducing the number of glitches in the global routing resources. The technique involves adding programmable delay elements within the logic block...
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ISBN:
(纸本)9781595936004
This paper describes a technique that reduces dynamic power in fpgas by reducing the number of glitches in the global routing resources. The technique involves adding programmable delay elements within the logic blocks of an fpga to programmably align the arrival times of early-arriving signals to the inputs of the lookup tables and to filter out glitches generated by earlier circuitry. On average, the proposed technique eliminates 91% of the glitching, which reduces overall fpga power by 18%. The added circuitry increases overall area by 5% and critical-path delay by less than 1%. Furthermore, since it is applied after routing, the proposed technique requires no modifications to the existing fpga routing architecture or CAD flow.
Since the inception of fpgas over 2 decades ago, the micro-architectures and macro-architectures of fpgas across all fpga vendors have been converging strongly to the point that comparable fpgas from the main fpga ven...
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ISBN:
(纸本)9781450370998
Since the inception of fpgas over 2 decades ago, the micro-architectures and macro-architectures of fpgas across all fpga vendors have been converging strongly to the point that comparable fpgas from the main fpga vendors had virtually the same use models, and the same programming models. User designs were getting easier to port from one vendor to the other with every generation. Recent developments in from different fpga vendors targeting the most advanced semiconductor technology nodes are an abrupt and disruptive break from this trend, especially at the macro-architectural level.
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