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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是691-700 订阅

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Optimizing SDRAM Bandwidth for Custom fpga Loop Accelerators 12

Optimizing SDRAM Bandwidth for Custom FPGA Loop Accelerators

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20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Bayliss, Samuel Constantinides, George A. Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn London SW7 2AZ England

ISBN: (纸本)9781450311557

Memory bandwidth is critical to achieving high performance in many fpga applications. The bandwidth of SDRAM memories is, however, highly dependent upon the order ill which addresses are presented on the SDRAM interface. We present an automated tool for constructing an application specific on-chip memory address sequencer which presents requests to the external memory with an ordering that optimizes off-chip memory bandwidth for fixed on-chip memory resource. Within a class of algorithms described by affine loop nests, this approach can be shown to reduce both the number of requests made to external memory and the overhead associated with those requests. Data presented shows a trade off between the use of on-chip resources and achievable off-chip memory bandwidth where a range of improvements from 3.6x to 4x gain in efficiency on the external memory interface can be gained at a cost of up to a 1.4 x increase in the ALUTs dedicated to address generation circuits in an Altera Stratix III device.

关键词： fpga Memory SDRAM Loop Transformations

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A Cycle-accurate, Cycle-reproducible multi-fpga System for Accelerating Multi-core Processor Simulation 12

A Cycle-accurate, Cycle-reproducible multi-FPGA System for A...

引用

20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Asaad, Sameh Bellofatto, Ralph Brezzo, Bernard Haymes, Chuck Kapur, Mohit Parker, Benjamin Roewer, Thomas Saha, Proshanta Takken, Todd Tierno, Jose IBM TJ Watson Res Ctr Yorktown Hts NY 10598 USA

ISBN: (纸本)9781450311557

Software based tools for simulation are not keeping up with the demands for increased chip and system design complexity. In this paper, we describe a cycle-accurate and cycle-reproducible large-scale fpga platform that is designed from the ground up to accelerate logic verification of the Bluegene/Q compute node ASIC, a multi-processor SOC implemented in IBM's 45 rim SOI CMOS technology. This paper discusses the challenges for constructing such large-scale fpga platforms, including design partitioning, clocking & synchronization, and debugging support, as well as our approach for addressing these challenges without sacrificing cycle accuracy and cycle reproducibility. The resulting fullchip simulation of the Bluegene/Q compute node ASIC runs at a simulated processor clock speed of 4 MHz, over 100,000 times faster than the logic level software simulation of the same design. The vast increase in simulation speed provides a new capability in the design cycle that proved to be instrumental in logic verification as well as early software development and performance validation for Bluegene/Q.

关键词： fpga Multi-core Logic Emulation

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Prototype and Evaluation of the CoRAM Memory Architecture for fpga-Based Computing 12

Prototype and Evaluation of the CoRAM Memory Architecture fo...

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20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Chung, Eric S. Papamichael, Michael K. Weisz, Gabriel Hoe, James C. Mai, Ken Carnegie Mellon Univ Comp Architecture Lab CALCM Pittsburgh PA 15213 USA

ISBN: (纸本)9781450311557

The CoRAM memory architecture for fpga-based computing augments traditional reconfigurable fabric with a natural and effective way for applications to interact with off-chip memory and I/O. The two central tenets of the CoRAM memory architecture are (1) the deliberate separation of concerns between computation versus data marshalling and (2) the use of a multithreaded software abstraction to replace FSM-based memory control logic. To evaluate the viability of the CoRAM memory architecture, we developed a full RTL implementation of a CoRAM microarchitecture instance that can be synthesized for standard cells or emulated on fpgas. The results of our evaluation show that a soft emulation of the CoRAM memory architecture on current fpgas can be impractical for memory-intensive, large-scale applications due to the high performance and area penalties incurred by the soft mechanisms. The results further show that in an envisioned fpga built with CoRAM in mind, the introduction of hard macro blocks for data distribution can mitigate these inefficiencies-allowing applications to take advantage of the CoRAM memory architecture for ease of programmability and portability while still enjoying performance and efficiency comparable to RTL-level application development on conventional fpgas.

关键词： fpga computing memory architecture

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Multi-Ported Memories for fpgas via XOR 12

Multi-Ported Memories for FPGAs via XOR

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20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： LaForest, Charles Eric Liu, Ming G. Rapati, Emma Rae Steffan, J. Gregory Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 1A1 Canada

ISBN: (纸本)9781450311557

Multi-ported memories are challenging to implement with fpgas since the block RAMs included in the fabric typically have only two ports. Any design that requires a memory with more than two ports must therefore be built out of logic elements or by combining multiple block RAMs. The recently-proposed Live Value Table (LVT) [8] design provides a significant operating frequency improvement over conventional approaches. In this paper we present an alternative approach based on the XOR operation that provides multi-ported memories that use far less logic but more block RAMs than LVT designs, and are often smaller and faster for memories that are more than 512 entries deep. We show that (i) both designs can exploit multipumping to trade speed for area savings, (ii) that multipumped XOR designs are significantly smaller but moderately slower than their LVT counterparts, and (iii) that both the LVT and XOR approaches are valuable and useful in different situations, depending on the constraints and resource utilization of the enclosing design.

关键词： fpga memory multi-port parallel XOR

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Compiling High Throughput Network Processors 12

Compiling High Throughput Network Processors

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20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Lavasani, Maysam Dennison, Larry Chiou, Derek Univ Texas Austin Austin TX 78712 USA

ISBN: (纸本)9781450311557

Gorilla is a methodology for generating fpga-based solutions especially well suited for data parallel applications with fine grain irregularity. Irregularity simultaneously destroys performance and increases power consumption on many data parallel processors such as General Purpose Graphical Processor Units (GPGPUs). Gorilla achieves high performance and low power through the use of fpga-tailored parallelizadon techniques and application-specific hardwired accelerators, processing engines, and communication mechanisms. Automatic compilation from a stylized C language and templates that define the hardware structure coupled with the intrinsic flexibility of fpgas provide high performance, low power, and programmability. Gorilla's capabilities are demonstrated through the generation of a family of core-router network processors processing up to 100Gbps (200MPPS for 64B packets) supporting any mix of IPv4, IPv6, and Multi-Protocol Label Switching (MPLS) packets on a single fpga with off-chip IP lookup tables. A 40Gbps version of that network processor was run with an embedded test rig on a Xilinx Virtex-6 fpga, verifying for performance and correctness. Its measured power consumption is comparable to full custom, commercial network processors. In addition, it is demonstrated how Gorilla can be used to generate merged virtual routers, saving fpga resources.

关键词： fpga network processor templates

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Exploiting algorithmic-level memory parallelism in distributed logic-memory architecture through hardware-assisted dynamic graph (abstract only) 13

Exploiting algorithmic-level memory parallelism in distribut...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Yu Bai Abigail Fuentes Mingjie Lin Mike Riera UCF Orlando FL USA University of Central Florida Orlando FL USA

ISBN: (纸本)9781450318877

Emerging fpga device, integrated with abundant RAM blocks and high-performance processor cores, offers an unprecedented opportunity to effectively implement single-chip distributed logic-memory (DLM) architectures. Being "memory-centric", the DLM architecture can significantly improve the overall performance and energy efficiency of many memory-intensive embedded applications, especially those that exhibit irregular array data access patterns at algorithmic level. However, implementing DLM architecture poses unique challenges to an fpga designer in terms of 1) organizing and partitioning diverse on-chip memory resources, and 2) orchestrating effective data transmission between on-chip and off-chip memory. In this paper, we offer our solutions to both of these challenges. Specifically, 1) we propose a stochastic memory partitioning scheme based on the well-known simulated annealing algorithm. It obtains memory partitioning solutions that promote parallelized memory accesses by exploring large solution space; 2) we augment the proposed DLM architecture with a reconfigure hardware graph that can dynamically compute precedence relationship between memory partitions, thus effectively exploiting algorithmic level memory parallelism on a per-application basis. We evaluate the effectiveness of our approach (A3) against two other DLM architecture synthesizing methods: an algorithmic-centric reconfigurable computing architectures with a single monolithic memory (A1) and the heterogeneous distributed architectures synthesized according to (A2). All experiments have been conducted with a Virtex-5 (XCV5LX155T-2) fpga. On average, our experimental results show that our proposed A3 architecture outperforms A2 and A1 by 34% and 250%, respectively. Within the performance improvement of A3 over A2, more than 70% improvement comes from the hardware graph-based memory scheduling.

关键词： fpga memory

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A Coarse-grained Stream Architecture for Cryo-electron Microscopy Images 3D Reconstruction 12

A Coarse-grained Stream Architecture for Cryo-electron Micro...

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20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Wang, Wendi Duan, Bo Tang, Wen Zhang, Chunming Tan, Guangming Zhang, Peiheng Sun, Ninghui Chinese Acad Sci Inst Comp Technol High Performance Comp Res Ctr Beijing Peoples R China

ISBN: (纸本)9781450311557

The wide acceptance and the data deluge in the bioinformatics and medical imaging processing require more efficient and application-specific systems to be built. Due to the recent advances in fpgas technologies, there has been a resurgence in research aimed at the design of special-purpose accelerators for standard computer architectures. In this paper, we exploit this trend towards fpga-based accelerator design and provide a proof-of-concept and comprehensive case study on fpga-based accelerator design for a single-particle 3D reconstruction application in single-precision floating-point format. The proposed stream architecture is built by first offloading computing-intensive software kernels to dedicated hardware modules, which emphasizes the importance of optimizing computing dominated data access patterns. Then configurable computing streams are constructed by arranging the hardware modules and bypass channels to form a linear deep pipeline. The efficiency of the proposed stream architecture is justified by the reported 2.54 times speedup over a 4-cores CPU. In terms of power efficiency, our fpga-based accelerator introduces a 7.33 and 3.4 times improvement over a 4-cores CPU and an up-to-date CPU device, respectively.

关键词： Cryo-electron microscopy FFT fpga stream processing memory access patterns

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A Configurable Architecture to Limit Wakeup Current in Dynamically-Controlled Power-gated fpgas 12

A Configurable Architecture to Limit Wakeup Current in Dynam...

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20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Bsoul, Assem A. M. Wilton, Steven J. E. Univ British Columbia Dept Elect & Comp Engn Vancouver BC V5Z 1M9 Canada

ISBN: (纸本)9781450311557

A dynamically-controlled power-gated (DCPG) fpga architecture has recently been proposed to reduce static energy dissipation during idle periods. During a power mode transition from an off state to on state, the wakeup current drawn from power supplies causes a voltage droop on the power distribution network of a device. If not handled appropriately, this current and the associated voltage droop could cause malfunction of the design and/or the device. In DCPG fpgas, the amount of wakeup current is not known beforehand as the structures of power-gated modules are application dependent;thus, a configurable solution is required to handle wakeup current. In this paper we propose a programmable wakeup architecture for DCPG fpgas. The proposed solution has two levels: a fixed intra-region level and a configurable inter-region level. The architecture ensures that a power-gated module can be turned on such that the wakeup current constraints are not violated. We study the area and power overheads of the proposed solution. Our results show that the area overhead of the proposed inrush current limiting architecture is less than 2% for a power gating region of size 3x3 or 4x4 tiles, and the leakage power saved is more than 85% in a region of size 4x4 tiles.

关键词： fpga Power Gating Architecture Inrush Current Leakage Power

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The VTR Project: Architecture and CAD for fpgas from Verilog to Routing 12

The VTR Project: Architecture and CAD for FPGAs from Verilog...

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20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Rose, Jonathan Luu, Jason Yu, Chi Wai Densmore, Opal Goeders, Jeffrey Somerville, Andrew Kent, Kenneth B. Jamieson, Peter Anderson, Jason Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 1A1 Canada

ISBN: (纸本)9781450311557

To facilitate the development of future fpga architectures and CAD - tools both embedded programmable fabrics and pure-play fpgas - there is a need for a large scale, publicly available software suite that can synthesize circuits into easily-described hypothetical fpga architectures. These circuits should be captured at the HIM, level, or higher, and pass through logical and physical synthesis. Such a tool must provide detailed modelling of area, performance and energy to enable architecture exploration. As software flows themselves evolve to permit design capture at ever higher levels of abstraction, this downstream full-implementation flow will always be required. This paper describes the current status and new release of an ongoing effort to create such a flow the 'Verilog to Routing' (VTR) project, which is a broad collaboration of researchers. There are three core tools: ODIN II [10] for Verilog Elaboration and front-end hard-block synthesis, ABC [16] for logic synthesis, and VPR [13] for physical synthesis and analysis. ODIN II now has a simulation capability to help verify that its output is correct, as well as specialized synthesis at the elaboration step for multipliers and memories. ABC is used to optimize the 'soft' logic of the fpga. The VPR-based packing, placement and routing is now fully timing-driven (the previous release was not) and includes new capability to target complex logic blocks. In addition we have added a set of four large benchmark circuits to a suite of previously-released Verilog HDL circuits. Finally, we illustrate the use of the new flow by using it to help architect a floating-point unit in an fpga., and contrast it with a prior, much longer effort that was required to do the same thing.

关键词： architecture fpga CAD

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CONNECT: Re-Examining Conventional Wisdom for Designing NoCs in the Context of fpgas 12

CONNECT: Re-Examining Conventional Wisdom for Designing NoCs...

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20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Papamichael, Michael K. Hoe, James C. Carnegie Mellon Univ Dept Comp Sci Pittsburgh PA 15213 USA

ISBN: (纸本)9781450311557

An fpga is a peculiar hardware realization substrate in terms of the relative speed and cost of logic vs. wires vs. memory. In this paper, we present a Network-on-Chip (NoC) design study from the mindset of NoC as a synthesizable infrastructural element to support emerging System-on-Chip (SoC) applications on fpgas. To support our study, we developed CONNECT, an NoC generator that;can produce synthesizable RTL designs of fpga-tuned multi-node NoCs of arbitrary topology. The CONNECT NoC architecture embodies a set of fpga-motivated design principles that uniquely influence key NoC design decisions, such as topology, link width, router pipeline depth, network buffer sizing, and flow control. We evaluate CONNECT against a high-quality publicly available synthesizable RTL-level NoC design intended for ASICs. Our evaluation shows a significant gain in specializing NoC design decisions to fpgas' unique mapping and operating characteristics. For example, in the case of a 4x4 mesh configuration evaluated using a set of synthetic traffic patterns, we obtain comparable or better performance than the state-of-the-art NoC while reducing logic resource cost by 58%, or alternatively, achieve 3-4x better performance for approximately the same logic resource usage. Finally, to demonstrate CONNECT's flexibility and extensive design space coverage, we also report synthesis and network performance results for several router configurations and for entire CONNECT networks.

关键词： Network-on-Chip NoC fpga System-on-Chip SoC

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