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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是701-710 订阅

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Rethinking fpgas: Elude the Flexibility Excess of LUTs with And-Inverter Cones 12

Rethinking FPGAs: Elude the Flexibility Excess of LUTs with ...

引用

20th acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Parandeh-Afshar, Hadi Benbihi, Hind Novo, David Ienne, Paolo Ecole Polytech Fed Lausanne Sch Comp & Commun Sci CH-1015 Lausanne Switzerland

ISBN: (纸本)9781450311557

Look-Up Tables (LUTs) are universally used in fpgas as the elementary logic blocks. They can implement any logic function and thus covering a circuit is a relatively straightforward problem. Naturally, flexibility comes at a price, and increasing the number of LUT inputs to cover larger parts of a circuit has an exponential cost in the LUT complexity. Hence, rarely LUTs with more than 4-6 inputs have been used. In this paper we argue that other elementary logic blocks can provide a better compromise between hardware complexity, flexibility, delay, and input and output counts. Inspired by recent trends in synthesis and verification, we explore blocks based on And-Inverter Graphs (AIGs): they have a complexity which is only linear in the number of inputs, they sport the potential for multiple independent outputs, and the delay is only logarithmic in the number of inputs. Of course, these new blocks are extremely less flexible than LUTs;yet, we show (i) that effective mapping algorithms exist, (ii) that, due to their simplicity, poor utilization is less of an issue than with LUTs, and (iii) that a few LUTs can still be used in extreme unfortunate cases. We show first results indicating that this new logic block combined to some LUTs in hybrid fpgas can reduce delay up to 22-32% and area by some 16% on average. Yet, we explored only a few design points and we think that these results could still be improved by a more systematic exploration.

关键词： fpga Logic Block Logic Synthesis And-Inverter Graph And-Inverter Cone

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acm/sigda international symposium on field programmable gate arrays - fpga: Foreword

ACM/SIGDA International Symposium on Field Programmable Gate...

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acm/sigda international symposium on field programmable gate arrays - fpga 2010年 iii页

作者： Cheung, Peter Wawrzynek, John Imperial College London United Kingdom University of California Berkeley CA United States

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Parallel fpga placement based on individual LUT placement (abstract only) 12

Parallel FPGA placement based on individual LUT placement (a...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Chris C. Wang Guy G.F. Lemieux University of British Columbia Vancouver BC Canada

ISBN: (纸本)9781450311557

This work describes a novel approach to fpga placement. Most conventional fpga CAD flow clusters circuits into CLBs prior to placing it. We show that is it possible to achieve 28% and 21% improvement in wirelength and minimum channel width respectively, while suffering only 1.8% in critical path delay by placing individual LUTs directly. By utilizing a good parallel placer, the novel approach can achieve speedups over the conventional uni-processor placers as well.

关键词： parallel placement fpga

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Timing yield improvement of fpgas utilizing enhanced architectures and multiple configurations under process variation (abstract only) 12

Timing yield improvement of FPGAs utilizing enhanced archite...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Fatemeh Sadat Pourhashemi Morteza Saheb Zamani Amirkabir University of Technology Tehran Iran

ISBN: (纸本)9781450311557

Designing with field-programmable gate arrays (fpgas) can face with difficulties due to process variations. Some techniques use reconfigurability of fpgas to reduce the effects of process variations in these chips. Furthermore, fpga architecture enhancement is an effective way to degrade the impact of variation. In this paper, various fpga architectures are examined to identify which architecture can achieve larger parametric yield improvement utilizing multiple configurations as opposed to single configuration. Experimental results show that by increasing cluster size from 4 to 10, yield improvement increases from 2.82X to 4.48X. However, changing look-up table (LUT) size from 4 to 7 results in yield improvement degradation from 2.82X to 1.45X, using 10 configurations compared to single configuration over 20 MCNC benchmark circuits. These results indicate that multi-configuration technique causes larger timing yield improvement in fpgas with larger cluster size and smaller LUT size.

关键词： multiple configurations fpga architecture process variation timing yield

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A novel full coverage test method for CLBs in fpga (abstract only) 12

A novel full coverage test method for CLBs in FPGA (abstract...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Yong Fu Chi Wang Liguang Chen Jinmei Lai Fudan University Shanghai China

ISBN: (纸本)9781450311557

fpga's configurability makes it difficult for fpga's manufacturers to fully test it. In this paper, a full coverage test method for fpga's Configurable Logic Blocks (CLBs) is proposed, through which all basic logics of fpga's every CLB can be fully tested. Innovative test circuits are configured to build repeatable logic arrays for look-up tables, distributed random access memories, configurable registers and other logics. The programmable interconnects needed to connect CLBs in these test circuits are also repeatable, making the configuration process much easier and the test speed much faster. The test method is implemented on different scales of Xilinx Virtex chips, where 19 test configuration circuits are needed to achieve 100% coverage for all CLBs. Besides, the method is transplantable and independent of fpga's array size. To evaluate the test method reliably and guide the process of test vectors generation, a fault simulator - Turbofault is used to simulate fpga's test coverage.

关键词： fault coverage test circuits design clb fpga

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Accelerating short read mapping on an fpga (abstract only) 12

Accelerating short read mapping on an FPGA (abstract only)

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Yupeng Chen Bertil Schmidt Douglas Leslie Maskell Nanyang Technological University Singapore Singapore Johannes Gutenberg University Mainz Mainz Germany

ISBN: (纸本)9781450311557

The explosive growth of short read datasets produced by high throughput DNA sequencing technologies poses a challenge to the mapping of short reads to a reference genome in terms of sensitivity and execution speed. Existing methods often use a restrictive error model for computing the alignments to improve speed, whereas more flexible error models are generally too slow for large-scale applications. Although a number of short read mapping software tools have been proposed, designs based on hardware are relatively rare. In this paper, we present a hybrid system for short read mapping utilizing both software and field programmable gate array (fpga)-based hardware. The compute intensive semi-global alignment operation is accelerated on the fpga. The proposed fpga aligner is implemented with a parallel block structure to gain computational efficiency. We also propose a block-wise alignment algorithm to approximate the score of the conventional dynamic programming algorithm. Our performance comparison shows that the fpga achieves an average speedup of 38 for the alignment operation on a Xilinx Virtex5 fpga compared to the GASSST software implementation. For the overall execution time, our hybrid system achieves an average speedup of 2.4 compared to GASSST at comparable sensitivity and an average speedup of 1.8 compared to the popular BWA software at a significantly better sensitivity.

关键词： short read alignment fpga parallel processing semi-global alignment hybrid system

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EmPower: fpga based emulation of dynamic power management algorithms for multi-core systems on chip (abstract only) 12

EmPower: FPGA based emulation of dynamic power management al...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Sundaram Ananthanarayanan Chirag Ravishankar Siddharth Garg Andrew Kennings Anna University Chennai India University of Waterloo Waterloo ON Canada

ISBN: (纸本)9781450311557

Dynamic power management for multi-core system on chip (MPSoC) platforms has become an increasingly critical design problem. In this paper, we present EmPower, an fpga based emulation, validation and prototyping framework for dynamic power management research targeted at MPSoC platforms. EmPower supports two advanced power management features -- per-core dynamic frequency scaling and clock gating, and power-aware thread migration. We also provide two fully-functional parallel applications for benchmarking -- video encoding and software-defined radio. Our experimental results indicate that EmPower provides up to 36 -- improvement in run-time compared to cycle-accurate software simulations, and enables accurate and efficient exploration of the design space of power management algorithms.

关键词： thread migration fpga implementation frequency scaling power management

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A field programmable array core for image processing (abstract only) 12

A field programmable array core for image processing (abstra...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Declan Walsh Piotr Dudek The University of Manchester Manchester United Kingdom

ISBN: (纸本)9781450311557

Massively parallel processor arrays have been shown to be an effective and suitable choice for image processing tasks [1]. More recently, some of the state of the art processor arrays have been used for real-time machine vision tasks such as intelligent transport system applications [2] or video processing on mobile applications [3] providing a much more powerful solution than a conventional processor. A number of Single Instruction Multiple Data (SIMD) processor arrays have been implemented on fpgas [4]-[6], which are particularly suited to implementing such processor architectures because of their similarities of both being arrays of fine grained logic elements. In this work, we propose an fpga implementation of a processor array where the processing elements (PEs) are as small as possible, while providing local memory sufficient for processing greyscale images. The PE is then replicated to form an array. A 32 × 32 PE array is implemented on a Xilinx Virtex 5 XC5VLX50 fpga using the four-neighbour connectivity with the possibility to scale up using a larger fpga. The processor array operates at a frequency of 96 MHz and executes a peak of 98.3 giga operations per second (GOPS) (bit-serial operations). A binary edge detection algorithm is performed in 52.08 ns. Uploading and downloading a binary image in a 32 × 32 array takes an extra 687.5 ns. Sobel edge detection of an 8-bit greyscale image is performed in 5.33 µs. Uploading and downloading an 8-bit greyscale image in a 32 × 32 array takes 5.36 µs. With larger fpgas being available in the future, the array sizes comparable to state of the art custom designed ICs can be implemented on these fpgas.

关键词： architecture fpga simd image processor array

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fpga-RR: an enhanced fpga architecture with RRAM-based reconfigurable interconnects (abstract only) 12

FPGA-RR: an enhanced FPGA architecture with RRAM-based recon...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Jason Cong Bingjun Xiao University of California at Los Angeles Los Angeles CA USA

ISBN: (纸本)9781450311557

In this study, we explore the use of Resistive RAMs (RRAMs) as candidates for programmable interconnects in fpgas. An RRAM cell can be programmed between high resistance state and low resistance state, with an on/off ratio close to MOSFET. It provides an opportunity to use an RRAM as a routing switch at a much smaller area cost than its CMOS counterpart. RRAMs can be fabricated over CMOS circuits using CMOS-compatible processes to have a more compact gate array. Our recent work (presented in NanoArch'2011) demonstrated significant potential of area, delay, and power reduction from using RRAMs in fpgas. But some design problems remain open. The programming of RRAM switches integrated in interconnects is one important problem. We show that the high-level architecture of programming circuits for RRAM switches should be modified to avoid potential logic hazard. Also the programming cells used in previous works have an area overhead even larger than RRAM itself. We manage to reduce this overhead significantly with utilization of the non-arbitrary pattern of RRAM integration in fpga interconnects. In addition we suggest a novel buffering solution for fpga interconnects in light of the low area cost of RRAM-based routing switch. We propose on-demand buffer insertion, where buffers can be connected to interconnects via RRAMs to dynamically reflect the demand of the netlist to map onto fpga. Compared to conventional buffering solution which are pre-determined during fabrication and can only be optimized for general case, our solution shows further area savings and performance improvement. The resulting fpga architecture using RRAM for programmable interconnects is named fpga-RR. We provide a complete CAD flow for fpga-RR.

关键词： resistive ram buffer programming rram fpga

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Power-aware fpga technology mapping for programmable-VT architectures (abstract only) 12

Power-aware FPGA technology mapping for programmable-VT arch...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Wei Ting Loke Yajun Ha Xilinx Asia Pacific Pte. Ltd. & National University of Singapore Singapore Singapore National University of Singapore Singapore Singapore

ISBN: (纸本)9781450311557

In this paper, we present a framework for leakage power reduction in fpgas with programmable-VT architectures, with focus on dual-VT technology mapping. The use of Reverse Back Bias (RBB) circuit techniques is recognized as one of the possible strategies in mitigating leakage power, a critical problem in circuits deploying deep submicron process technologies. fpgas with the ability to tune LUT VT via RBB offer the potential of reducing leakage power with no sacrifice to circuit speed. Today, Altera's Stratix line of fpgas oer some levels of VT programmability, but with optimizations limited to the post-P&R stage. We present a novel technology mapper (RBBMap), logic block packer (RBBPack) and placement-and-routing tool (RBBVPR) that together demonstrate the advantages in moving RBB optimizations upwards to the technology mapping level. Compared to an existing power-optimized technology mapping tool Emap, our framework oers an average of 44.41% savings in average logic block leakage power and 30.88% savings in average total energy consumption. We also illustrate why our work is potentially superior to another comparable work DVMap-2 that utilizes a dual-VDD approach.

关键词： fpga multiple voltage programmable-vt dual-vt reverse back bias technology mapping

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