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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是711-720 订阅

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Adaptive fpga-based robotics state machine architecture derived with genetic algorithms (abstract only) 12

Adaptive FPGA-based robotics state machine architecture deri...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Jesus Savage Rodrigo Savage Marco Morales-Aguirre Angel Kuri-Morales Universidad Nacional Autonoma de Mexico Mexico City Mexico Instituto Tecnologico Autonomo de Mexico Mexico City Mexico

ISBN: (纸本)9781450311557

This paper discusses how to generate mobile robots' behaviors using genetic algorithms, GA. The behaviors are built using state machines implemented in a programmable logic device, an fpga, and they are encoded in such a way that a state machine architecture executes them, controlling the overall operation of a small mobile robot. The behaviors generated by the GA are evaluated according to a fitness function that grades their performance. Basically, the fitness function evaluates the robot's performance when it goes from an origin to a destination. In our approach each individuals' chromosome represents, given a set of inputs coming from the sensors and the current state, the next state and outputs that controls the robot's movements. For each generation the GA needs to evaluate population's individuals, doing this with the real robot it would required to much time, that would be impossible to do. Thus, the GA needs a simulator, as close as it can be to the real robot and its environment. The simulator gets the individuals' chromosomes and executes the algorithm state machine represented by them, it simulates the movements of the robot depending of the output generated in the present state and the simulated robot's sensors. Our objective was to prove that GA is a good option as a method for finding behaviors for mobile robots' navigation and also that these behaviors can be implemented in fpgas.

关键词： robots behaviors genetic algorithms

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The masala machine: accelerating thread-intensive and explicit memory management programs with dynamically reconfigurable fpgas (abstract only) 12

The masala machine: accelerating thread-intensive and explic...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Mei Wen Nan Wu Qianming Yang Chunyuan Zhang Liang Zhao National University of Defense Technology Changsha China

ISBN: (纸本)9781450311557

A uniform fpga-based architecture, an efficient programming model and a simple mapping method are paramount for PPGA technology to be more widely accepted. This paper presents MASALA, a dynamically reconfigurable fpga-based accelerator specifically for parallel programs written in thread-intensive and explicit memory management (TEMM) programming models. The system uses TEMM programming model to parallelize the demanding application, including decomposing the application into separate thread blocks, decoupling compute and data load/store etc. Hardware engines are included into the MASALA by using partial dynamic reconfigure modules, each of which encapsulates Thread Process Engine implementing the thread functionality in hardware. A data dispatching scheme is also included in MASALA to enable the explicit communication among multiple memory hierarchies such as between inter-hardware engines, the host processor and hardware engines. At last, the paper illustrates a Multi-fpga prototype system of the presented architecture: MASALA-SX. A large synthetic aperture radar (SAR) image formatting experiment shows that the MASALA architecture facilitates the construction of a TEMM program accelerator by providing it with greater performance and less power consumption than current CPU platforms, but without sacrificing programmability, flexibility and scalability.

关键词： accelerator thread-intensive masala explicit memory management fpga sar

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Algorithm and architecture optimization for large size two dimensional discrete fourier transform (abstract only) 12

Algorithm and architecture optimization for large size two d...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Berkin Akin Peter A. Milder Franz Franchetti James C. Hoe Carnegie Mellon University Pittsburgh PA USA

ISBN: (纸本)9781450311557

We present a poster showcasing our fpga implementations of two-dimensional discrete Fourier transform (2D-DFT) on large datasets that must reside off-chip in DRAM. These memory-bound large 2D-DFT computations are at the heart of important scientific computing and image processing applications. The central challenge in creating high-performance implementations is in the carefully orchestrated use of the available off-chip memory bandwidth and on-chip temporary storage. Our implementations derive their efficiency from a combined attention to both the algorithm design to enable efficient DRAM access patterns and datapath design to extract the maximum compute throughput at a given level of memory bandwidth. The poster reports results including a 1024x1024 double-precision 2D-DFT implementation on an Altera DE4 platform (based on a Stratix IV EP4SGX530 with 12 GB/s DRAM bandwidth) that reached over 16 Gflop/s, achieving a much higher ratio of performance-to-memory-bandwidth than both state-of-the-art CPU and GPU implementations.

关键词： bandwidth fft 2d-dft dram fpga

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Operation scheduling and architecture co-synthesis for energy-efficient dataflow computations on fpgas (abstract only) 12

Operation scheduling and architecture co-synthesis for energ...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Colin Yu Lin Ngai Wong Hayden Kwok-Hay So The University of Hong Kong Hong Kong Hong Kong

ISBN: (纸本)9781450311557

Compiling high-level user applications for execution on fpgas often involves synthesizing dataflow graphs beyond the size of the available on-chip computational resources. One way to address this is by folding the execution of the given dataflow graphs onto an array of directly connected simple configurable processing elements (CPEs). Under this scenario, the performance and energy-efficiency of the resulting system depends not only on the mapping schedule of the compute operations on the CPEs, but also on the topology of the interconnect array that connects the CPEs. This paper presents a framework in which the operation scheduler and the underlying CPE interconnect network topology are co-optimized on a per-application basis for energy-efficient fpga computation. Given the same application, more than 2.5x difference in energy-efficiency was achievable by the use of different common regular array topologies to connect the CPEs. Moreover, by using irregular application-specific interconnect topologies derived from a genetic algorithm, up to 50% improvement in energy-delay-product was achievable when compared to the use of even the best regular topology. The use of such framework is anticipated to serve as part of a rapid high-level fpga application compiler since minimum hardware place-and-route is needed to generate the optimal schedule and topology.

关键词： fpga dataflow computation architecture synthesis energy-efficient operation scheduling

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OpenCL memory infrastructure for fpgas (abstract only) 12

OpenCL memory infrastructure for FPGAs (abstract only)

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： S. Alexander Chin Paul Chow University of Toronto Toronto ON Canada

ISBN: (纸本)9781450311557

Programming models assist developers in creating high performance computing systems by forming a higher level abstraction of the target platform. OpenCL has emerged as a standard programming model for heterogeneous systems and there has been recent activity combining OpenCL and fpgas. This work introduces memory infrastructure for fpgas and is designed for OpenCL style computation, complementing previous work. An Aggregating Memory Controller is implemented in hardware and aims to maximize bandwidth to external, large, high-latency, high-bandwidth memories by finding the minimal number of external memory burst requests from a vector of requests. A template processing array with soft-processor and hand-coded hardware elements was also designed to drive the memory controller. The Aggregating Memory Controller is described in terms of operation and future scalability and the created processing array is described as a flexible structure that can support many types of processing solutions. A hardware prototype of the memory controller and processing array was implemented on a Virtex-5 LX110T fpga. Two micro-benchmarks were run on both the soft-processor elements and the hand-coded hardware cores to exercise the memory controller. Results for effective memory bandwidth within the system show that the high-latency can be hidden using the Aggregating Memory Controller by increasing the number of threads within the processing array.

关键词： memory aggregation opencl dram fpga memory coalescing

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Efficient in-system RTL verification and debugging using fpgas (abstract only) 12

Efficient in-system RTL verification and debugging using FPG...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Proshanta Saha Chuck Haymes Ralph Bellofatto Bernard Brezzo Mohit Kapur Sameh Asaad IBM T.J. Watson Research Center Yorktown Heights NY USA IBM T. J. Watson Research Center Yorktown Heights NY USA

ISBN: (纸本)9781450311557

fpgas have become indispensible in processor design, bring-up and debug. Traditionally fpgas have been used in prototyping, allowing end-users to emulate functionality of a specific component of a processor. However, as the complexity of processors grows, another aspect of processor design, RTL verification, has become a prime target for acceleration using fpgas. Software-only RTL simulation and verification tools are no longer sufficient for many verification tasks as they often incur long execution time penalties. Software simulation time for a basic Linux kernel bring-up on a BlueGene/Q [1] processor, with 16 user PowerPC A2 cores, for example, could easily exceed several *** important feature of RTL verification acceleration using fpgas is its fast debugging capabilities. The ability to quickly and accurately pinpoint the location of an anomaly in an RTL source is highly desirable. This paper proposes efficient in-system debugging techniques on fpgas for RTL verification. We show how a network of over 45 Virtex 5 LX330 fpgas can be efficiently used to read out state information of the BlueGene/Q processor. We also demonstrate how the new in-system debugging technique is 250x faster than comparable methods.

关键词： fpga debugging fpga-based acceleration processor simulation

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Thermal and Power Characterization of field-programmable gate arrays 11

Thermal and Power Characterization of Field-Programmable Gat...

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19th Annual acm international symposium on field-programmable gate arrays

作者： Nowroz, Abdullah Nazma Reda, Sherief Brown Univ Sch Engn Providence RI 02912 USA

ISBN: (纸本)9781450305549

In this paper we propose new techniques for thermal and power characterization of field programmable gate arrays (fpgas) using infrared imaging techniques. For thermal characterization, we capture the thermal emissions from the backside of an fpga chip during operation. We analyze the captured emissions and quantify the extent of thermal gradients and hot spots in fpgas. Given that fpgas are fabricated with no knowledge of the potential field designs, we propose soft sensing techniques that can combine the measurements of hard sensors to accurately estimate the temperatures where no sensors are embedded. For power characterization, we propose algorithmic techniques to invert the thermal emissions from fpgas into spatial power estimates. We demonstrate how this technique can be used to produce spatial power maps of soft processors during operation.

关键词： Thermal characterization sensors power mapping

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An Analytical Model Relating fpga Architecture Parameters to Routability 11

An Analytical Model Relating FPGA Architecture Parameters to...

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19th Annual acm international symposium on field-programmable gate arrays

作者： Das, Joydip Wilton, Steven J. E. Univ British Columbia Vancouver BC V5Z 1M9 Canada

ISBN: (纸本)9781450305549

We present an analytical model relating fpga architectural parameters to the routability of the fpga. The inputs to the model include the channel width and connection and switch block flexibilities, and the output is an estimate of the proportion of nets in a large circuit that can be expected to be routed on the fpga. We assume that the circuit is routed to the fpga using a single-step combined global/detailed router. Together with the earlier works on analytical modeling, our model can be used to predict the routability without going through an expensive CAD flow. We show that the model correctly predicts routability trends.

关键词： fpga Analytical Model Architecture Development Routability

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Early timing estimation for system-level design using fpgas (abstract only) 12

Early timing estimation for system-level design using FPGAs ...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Hugo Andrade Arkadeb Ghosal Rhishikesh Limaye Sadia Malik Newton Petersen Kaushik Ravindran Trung Tran Guoqiang Wang Guang Yang National Instruments Corp. Berkeley CA USA National Instruments Corp. Austin TX USA

ISBN: (纸本)9781450311557

fpga devices provide flexible, fast, and low-cost prototyping and production solutions for system design. However, as the design complexity continues to rise, the design and synthesis iterations become a labor intensive and time consuming ordeal. Consequently, it becomes imperative to raise the level of abstraction for fpga designs, while providing insight into performance metrics early in the design process. In particular, an important design time problem is to determine the maximum clock frequency that a circuit can achieve on a specific fpga target before full synthesis and implementation. This early quantification can greatly help evaluate key design characteristics without reverting to tedious runs of the full implementation flow. In this work, we focus on the predictability of timing delay of circuits composed of high-level blocks on an fpga. We are well aware of difficulties in tackling uncertainties in early timing estimation, e.g., an inherent gap between a high-level representation and gates/wires; extremely difficult delay estimation due to the randomness in physical design tools, etc. We show that the estimation uncertainties can be mitigated through a carefully characterized timing database of primitive building blocks and refined timing analysis models. We primarily focus on applications composed of data-intensive word-level arithmetic computations from the DSP domain and specified using static dataflow models. Our experiments indicate that for these applications, timing estimates can be obtained reliably within a good error margin on average and in the worst case. As future work, we plan to fine tune the timing database by modeling resource utilization effects and inter-primitive/actor routing delay via variants of Rent's rule and related efforts. We are also interested in exploring dynamic sub-cycle timing characterization.

关键词： early timing analysis fpga system-level design

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Authenticated Encryption for fpga Bitstreams 11

Authenticated Encryption for FPGA Bitstreams

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19th Annual acm international symposium on field-programmable gate arrays

作者： Trimberger, Steve Moore, Jason Lu, Weiguang Xilinx Inc San Jose CA 95124 USA

ISBN: (纸本)9781450305549

fpga bitstream encryption blocks theft of the design in the fpga bitstream by preventing unauthorized copy and reverse engineering. By itself, encryption does not protect against tampering with the bitstream, so without additional capabilities, bitstream encryption cannot prevent the fpga from executing an unauthorized bitstream. An unauthorized bitstream might be generated by trial and error to cause the fpga to leak confidential data, including the decrypted bitstream. Strong authentication detects tampering with the bitstream, providing a root of trust that enables applications that require protection of sensitive data in a hostile environment. This paper describes the SHA HMAC-based bitstream authentication algorithm and protocol in Virtex-6 fpgas and shows how they are integrated in the bitstream.

关键词： fpga bitstream encryption authentication trust trusted design self-reconfiguration

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