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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是731-740 订阅

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A Platform for High Level Synthesis of Memory-Intensive Image Processing Algorithms 11

A Platform for High Level Synthesis of Memory-Intensive Imag...

引用

19th Annual acm international symposium on field-programmable gate arrays

作者： Papenfuss, Tim Michel, Holger Fraunhofer Inst Integrated Circuits D-91058 Erlangen Germany

ISBN: (纸本)9781450305549

For high-end industrial image processing applications with real-time requirements, fpgas are often used as custom accelerators. High level synthesis tools, such as CatapultC, provide a compelling means of speeding up the algorithmic hardware design. However, increasing image resolutions make it ever more difficult to obtain sufficient throughput from external SDRAM frame buffers while providing simple, low-latency memory resources for the data path. To address these issues, this paper proposes a platform-based design with a custom memory system of buffers, caches and an optimized commercial memory controller that improves available SDRAM bandwidth by up to 4x. This greatly facilitates the high level synthesis flow, which is demonstrated by implementing two memory-intensive algorithms using 47.0 Gbit/s and 5.7 Gbit/s of on-chip and off-chip memory bandwidth respectively.

关键词： SDRAM fpga high level synthesis image processing

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CoRAM: An In-Fabric Memory Architecture for fpga-based Computing 11

CoRAM: An In-Fabric Memory Architecture for FPGA-based Compu...

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19th Annual acm international symposium on field-programmable gate arrays

作者： Chung, Eric S. Hoe, James C. Mai, Ken Carnegie Mellon Univ Pittsburgh PA 15213 USA

ISBN: (纸本)9781450305549

fpgas have been used in many applications to achieve orders-of-magnitude improvement in absolute performance and energy efficiency relative to conventional microprocessors. Despite their promise in both processing performance and efficiency, fpgas have not yet gained widespread acceptance as mainstream computing devices. A fundamental obstacle to fpga-based computing today is the fpga's lack of a common, scalable memory architecture. When developing applications for fpgas, designers are often directly responsible for crafting the application-specific infrastructure logic that manages and transports data to and from the processing kernels. This infrastructure not only increases design time and effort but will frequently lock a design to a particular fpga product line, hindering scalability and portability. We propose a new fpga memory architecture called Connected RAM (CoRAM) to serve as a portable bridge between the distributed computation kernels and the external memory interfaces. In addition to improving performance and efficiency, the CoRAM architecture provides a virtualized memory environment as seen by the hardware kernels to simplify development and to improve an application's portability and scalability.

关键词： fpga abstraction memory reconfigurable computing

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LEAP Scratchpads: Automatic Memory and Cache Management for Reconfigurable Logic 11

LEAP Scratchpads: Automatic Memory and Cache Management for ...

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19th Annual acm international symposium on field-programmable gate arrays

作者： Adler, Michael Fleming, Kermin E. Parashar, Angshuman Pellauer, Michael Emer, Joel Intel Corp VSSAD Grp Santa Clara CA 95051 USA

ISBN: (纸本)9781450305549

Developers accelerating applications on fpgas or other reconfigurable logic have nothing but raw memory devices in their standard toolkits. Each project typically includes tedious development of single-use memory management. Software developers expect a programming environment to include automatic memory management. Virtual memory provides the illusion of very large arrays and processor caches reduce access latency without explicit programmer instructions. LEAP scratchpads for reconfigurable logic dynamically allocate and manage multiple, independent, memory arrays in a large backing store. Scratchpad accesses are cached automatically in multiple levels, ranging from shared on-board, RAM-based, set-associative caches to private caches stored in fpga RAM blocks. In the LEAP framework, scratchpads share the same interface as on-die RAM blocks and are plug-in replacements. Additional libraries support heap management within a storage set. Like software developers, accelerator authors using scratchpads may focus more on core algorithms and less on memory management.

关键词： fpga memory management caches

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Automatic SoC Design Flow on Many-core Processors: a Software Hardware Co-Design Approach for fpgas 11

Automatic SoC Design Flow on Many-core Processors: a Softwar...

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19th Annual acm international symposium on field-programmable gate arrays

作者： Liu, Ling Morozov, Oleksii Han, Yuxing Gutknecht, Juerg Hunziker, Patrick ETH Inst Comp Syst CH-8092 Zurich Switzerland

ISBN: (纸本)9781450305549

Traditional fpga-based system-on-chip (SoC) design in general is accomplished via separate software and hardware design flows. With such a separate design methodology, extra development overhead has to be paid to meet the final system's performance, size and power consumption requirements. To overcome this development overhead which usually leads to significant increase of the time-to-market, a unified and efficient SoC design flow is needed. The current work addresses this problem via a SoC design flow which allows automatic building of a complete autonomous system on an fpga in accordance with the need of a specific application. In the proposed design flow the architecture of the generated hardware is tailored to match the parallelism granularity and communication structure of the application. This, in turn, allows the application developer to meet the system's performance, size and power consumption requirements with a short time-to-market. To prove the applicability of the proposed approach, a monitor for real-time electrocardiographic (ECG) signal analysis and a motion detection algorithm have been implemented.

关键词： automatic design flow many-core architecture software-hardware co-design fpga

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Real-time high-definition stereo matching on fpga 11

Real-time high-definition stereo matching on FPGA

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Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Zhang, Lu Zhang, Ke Chang, Tian Sheuan Lafruit, Gauthier Kuzmanov, Georgi Krasimirov Verkest, Diederik Delft University of Technology Mekelweq 4 2600GA Delft Netherlands IMEC Kapeldreef 75 B-3001 Leuven Belgium National Chiao Tung University 1001 TaHsueh Rd. Hsinchu Taiwan

ISBN: (纸本)9781450305549

Although many fast stereo matching designs have been proposed in the past decades, it is still very challenging to achieve real-time speed at high definition resolution while maintaining high matching accuracy. In this paper, we propose a real-time high definition stereo matching design on fpga. By using the Mini-Census transform and the Cross-based cost aggregation, the proposed algorithm is robust to radiometric differences and produces accurate disparity maps. The algorithm modules have been optimized for efficient hardware implementations and instantiated in an SoC environment. Implemented on a single EP3SL150 fpga, our design achieves 60 frames per second for 1024 × 768 stereo images. Evaluated with the Middlebury stereo benchmark, the proposed design also delivers leading stereo matching accuracy among prior related work. Copyright 2011 acm.

关键词： field programmable gate arrays (fpga)

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A CAD Framework for MALIBU: An fpga with Time-multiplexed Coarse-Grained Elements 11

A CAD Framework for MALIBU: An FPGA with Time-multiplexed Co...

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19th Annual acm international symposium on field-programmable gate arrays

作者： Grant, David Wang, Chris Lemieux, Guy G. F. Univ British Columbia Dept Elect & Comp Engn Vancouver BC V5Z 1M9 Canada

ISBN: (纸本)9781450305549

Modern fpgas are used to implement a wide range of circuits, many of which have coarse-grained and fine-grained components. The ever-increasing size of these circuits places great demand on CAD tools to synthesize circuits faster and without loss in quality. Synthesizing coarse-grained components onto fine-grained fpga resources is inefficient, and past attempts to optimize fpgas for word-oriented datapaths have met with limited success. This paper presents a CAD flow to fully compile Verilog into a configuration bitstream for a new type of fpga with time-multiplexed coarse-grained resources. We demonstrate two approaches with gains of 61x and 42x in synthesis time on average compared to QuartusII, but due to time-multiplexing and current synthesis limitations we achieve circuit speeds of 14x and 8.5x slower on average. We show the tools can also trade density for maximum clock frequency.

关键词： Algorithms Design Performance

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LegUp: High-level synthesis for fpga-based processor/accelerator systems 11

LegUp: High-level synthesis for FPGA-based processor/acceler...

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Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Canis, Andrew Choi, Jongsok Aldham, Mark Zhang, Victor Kammoona, Ahmed Anderson, Jason H. Brown, Stephen Czajkowski, Tomasz ECE Department University of Toronto Toronto ON Canada Altera Toronto Technology Centre Altera Corp. Toronto ON Canada

ISBN: (纸本)9781450305549

In this paper, we introduce a new open source high-level synthesis tool called LegUp that allows software techniques to be used for hardware design. LegUp accepts a standard C program as input and automatically compiles the program to a hybrid architecture containing an fpga-based MIPS soft processor and custom hardware accelerators that communicate through a standard bus interface. Results show that the tool produces hardware solutions of comparable quality to a commercial high-level synthesis tool. Copyright 2011 acm.

关键词： High level synthesis

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A 65nm Flash-Based fpga Fabric Optimized for Low Cost and Power 11

A 65nm Flash-Based FPGA Fabric Optimized for Low Cost and Po...

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19th Annual acm international symposium on field-programmable gate arrays

作者： Greene, Jonathan Kaptanoglu, Sinan Feng, Wenyi Hecht, Volker Landry, Joel Li, Fei Krouglyanskiy, Anton Morosan, Mihai Pevzner, Val Microsemi Corp SOC Prod Grp Mountain View CA 94043 USA

ISBN: (纸本)9781450305549

This paper describes a non-volatile reprogrammable fpga fabric, whose configuration data are provided directly by flash memory. The fabric is optimized for low-cost, low-power applications, leveraging the density of flash and the elimination of conventional configuration SRAM and its attendant static power. After surveying the necessary background on flash and its application to fpgas, the IT flash cell is described along with relevant novel aspects of the fabric architecture. The addition of a third level of switching between inter-cluster signals and logic inputs helps to reduce area and raise typical utilization above 95%. Despite the longer signal path, performance is maintained by synergism between the improved routing flexibility and extreme minimization of the fastest LUT input delay. Test cost is reduced by built-in circuits that can test all switches without reprogramming the flash memory. The fabric has been implemented in a 65nm CMOS embedded flash process.

关键词： fpga architecture flash memory Clos network built-in self-test programmable routing input interconnection block IIB packing

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Memory-Efficient and Scalable Virtual Routers Using fpga 11

Memory-Efficient and Scalable Virtual Routers Using FPGA

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19th Annual acm international symposium on field-programmable gate arrays

作者： Le, Hoang Ganegedara, Thilan Prasanna, Viktor K. Univ So Calif Ming Hsieh Dept Elect Engn Los Angeles CA 90089 USA

ISBN: (纸本)9781450305549

Router virtualization has recently gained much interest in the research community. It allows multiple virtual router instances to rim on a common physical router platform. The key metrics in designing network virtual routers are: (1) number of supported virtual router instances, (2) total number of prefixes, and (3) ability to quickly update the virtual table. Limited on-chip memory in fpga leads to the need for memory-efficient merging algorithms. On the other hand, due to high frequency of combined updates from all the virtual routers, the merging algorithms must be highly efficient. Hence, the router must support quick updates. In this paper, we propose a simple merging algorithm whose performance is not sensitive to the number of routing tables considered. The performance solely depends on the total number of prefixes. We also propose a novel scalable, high-throughput linear pipeline architecture for IP-lookup that supports large virtual routing tables and quick non-blocking update. Using a state-of-the-art field programmable gate Array (fpga) along with external SRAM, the proposed architecture can support up to 16M IPv4 and 880K IPv6 prefixes. Our implementation shows a sustained throughput of 400 million lookups per second, even when external SRAM is used.

关键词： fpga IP Lookup Virutal Routers Pipeline

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Building a Multi-fpga Virtualized Restricted Boltzmann Machine Architecture Using Embedded MPI 11

Building a Multi-FPGA Virtualized Restricted Boltzmann Machi...

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19th Annual acm international symposium on field-programmable gate arrays

作者： Lo, Charles Chow, Paul Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada

ISBN: (纸本)9781450305549

Several fpga architectures exist for accelerating Restricted Boltzmann Machines (RBMs). However, the network size for most is limited by the amount of available on-chip memory. Therefore, many fpgas are required to implement very large networks for use in real-world applications. A virtualized design is able to time-multiplex the hardware resources and handle much larger networks but suffers a performance penalty due to the context switch. In this paper, we present a number of improvements to a virtualized fpga architecture for RBMs. First, we take advantage of 16-bit arithmetic to pack larger networks onto a chip. Second, a custom DMA engine is designed to reduce the performance impact of the large amount of memory transactions. Finally, the architecture is scaled to multiple fpgas to gain additional performance through coarse grain parallelism. The design effort required to implement these changes is minimized through the use of an embedded MPI framework. The architecture, tested on a Berkeley Emulation Engine 3 platform running at 100 Mhz, achieves a speed of 12.563 GCUPS on a 8192x8192 network.

关键词： Restricted Boltzmann Machines Neural Network Hardware fpga High Performance Computing

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