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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是741-750 订阅

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An fpga Implementation of a Sparse Quadratic Programming Solver for Constrained Predictive Control 11

An FPGA Implementation of a Sparse Quadratic Programming Sol...

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19th Annual acm international symposium on field-programmable gate arrays

作者： Jerez, Juan L. Constantinides, George A. Kerrigan, Eric C. Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn London SW7 2AZ England

ISBN: (纸本)9781450305549

Model predictive control (MPC) is an advanced industrial control technique that relies on the solution of a quadratic programming (QP) problem at every sampling instant to determine the input action required to control the current and future behaviour of a physical system. Its ability in handling large multiple input multiple output (MIMO) systems with physical constraints has led to very successful applications in slow processes, where there is sufficient time for solving the optimization problem between sampling instants. The application of MPC to faster systems, which adds the requirement of greater sampling frequencies, relies on new ways of finding faster solutions to QP problems. field-programmable gate arrays (fpgas) are specially well suited for this application due to the large amount of computation for a small amount of I/O. In addition, unlike a software implementation, an fpga can provide the precise timing guarantees required for interfacing the controller to the physical system. We present a high-throughput floating-point fpga implementation that exploits the parallelism inherent in interior-point optimization methods. It is shown that by considering that the QPs come from a control formulation, it is possible to make heavy use of the sparsity in the problem to save computations and reduce memory requirements by 75%. The implementation yields a 6.5x improvement in latency and a 51x improvement in throughput for large problems over a software implementation running on a general purpose microprocessor.

关键词： optimization interior-point model predictive control

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Scalable and deterministic timing-driven parallel placement for fpgas 11

Scalable and deterministic timing-driven parallel placement ...

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Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Wang, Chris C. Lemieux, Guy G.F. Dept. of ECE University of British Columbia Vancouver BC Canada

ISBN: (纸本)9781450305549

This paper describes a parallel implementation of the timing-driven VPR∼5.0 simulated annealing engine. By restricting the move distance to a confined neighborhood, it is possible to consider a large number of non-conflicting moves in parallel and achieve a deterministic result. The full timing-driven algorithm is parallelized, including the detailed timing analysis updates done periodically while placement progresses. The limited move slightly degrades the placement quality, but this is necessary to expose greater degrees of parallelism. The overall bounding box metric degrades about 11% and critical path delay metric degrades about 8% compared to VPR's original algorithm, but we show the amount of degradation is independent of the number of threads. Overall, the parallel implementation scales to a speedup of 123× using 25 threads compared to VPR. With additional tuning effort, we believe the algorithm can be scaled to a larger number of threads, perhaps even run on a GPU, with little additional quality degradation. Copyright 2011 acm.

关键词： field programmable gate arrays (fpga)

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Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect 11

Architecture description and packing for logic blocks with h...

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Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Luu, Jason Anderson, Jason Helge Rose, Jonathan Scott Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto Toronto ON Canada

ISBN: (纸本)9781450305549

The development of future fpga fabrics with more sophisticated and complex logic blocks requires a new CAD flow that permits the expression of that complexity and the ability to synthesize to it. In this paper, we present a new logic block description language that can depict complex intra-block interconnect, hierarchy and modes of operation. These features are necessary to support modern and future fpga complex soft logic blocks, memory and hard blocks. The key part of the CAD flow associated with this complexity is the packer, which takes the logical atomic pieces of the complex blocks and groups them into whole physical entities. We present an area-driven generic packing tool that can pack the logical atoms into any heterogeneous fpga described in the new language, including many different kinds of soft and hard logic blocks. We gauge its area quality by comparing the results achieved with a lower bound on the number of blocks required, and then illustrate its explorative capability in two ways: on fracturable LUT soft logic architectures, and on hard block memory architectures. The new infrastructure attaches to a flow that begins with a Verilog front-end, permitting the use of benchmarks that are significantly larger than the usual ones, and can target heterogenous fpgas. Copyright 2011 acm.

关键词： field programmable gate arrays (fpga)

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Co-synthesis of fpga-Based Application-Specific Floating Point SIMD Accelerators 11

Co-synthesis of FPGA-Based Application-Specific Floating Poi...

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19th Annual acm international symposium on field-programmable gate arrays

作者： Hagiescu, Andrei Wong, Weng-Fai Natl Univ Singapore Sch Comp Singapore 117548 Singapore

ISBN: (纸本)9781450305549

The constant push for feature richness in mobile and embedded devices has significantly increased computational demand. However, stringent energy constraints typically remain in place. Embedding processor cores in fpgas offers a path to having customized instruction processors that can meet the performance and energy demands. Ideally, the customization process should be automated to reduce the design effort, and indirectly the time to market. However, the automatic generation of custom extensions for floating point computation remains a challenge in fpga co-design. We propose an approach for accelerating such computation via application-specific SIMD extensions. We describe an automated co-design toolchain that generates code and application-specific platform extensions that implement SIMD instructions with a parameterizable number of vector elements. The parallelism exposed by encapsulating computation in vector instructions is matched to an adjustable pool of execution units. Experiments on actual hardware show significant performance improvements. Our framework provides an important extension to the capabilities of embedded processor fpgas which traditionally dealt with bit, integer, and low intensity floating point code, to now being able to handle vectorizable floating point computation.

关键词： Co-synthesis Custom instructions SIMD

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Bridging the GPGPU-fpga efficiency gap 11

Bridging the GPGPU-FPGA efficiency gap

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Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Fletcher, Christopher W. Lebedev, Ilia A. Asadi, Narges B. Burke, Daniel R. Wawrzynek, John CSAIL Massachusetts Institute of Technology Cambridge MA United States EECS Dept. University of California Berkeley CA United States EE Dept. Stanford University Stanford CA United States

ISBN: (纸本)9781450305549

This paper compares an implementation of a Bayesian inference algorithm across several fpgas and GPGPUs, while embracing both the execution model and high-level architecture of a GPGPU. Our study is motivated by recent work in template-based programming and architectural models for fpga computing. The comparison we present is meant to demonstrate the fpga's potential, while constraining the design to follow the microarchitectural template of more programmable devices such as GPGPUs. The fpga implementation proves capable of matching the performance of a high-end Nvidia Fermi-based GPU - the most advanced GPGPU available to us at the time of this study. Further investigation shows that each fpga core outperforms workstation GPGPU cores by a factor of ∼ 3.14×, and mobile GPGPU cores by ∼ 4.25× despite a ∼ 4× reduction in core clock frequency. Using these observations, we discuss the efficiency gap between these two platforms, and the challenges associated with template-based programming models. Copyright 2011 acm.

关键词： Bayesian networks

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Comparing fpga vs. Custom CMOS and the Impact on Processor Microarchitecture 11

Comparing FPGA vs. Custom CMOS and the Impact on Processor M...

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19th Annual acm international symposium on field-programmable gate arrays

作者： Wong, Henry Betz, Vaughn Rose, Jonathan Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 1A1 Canada

ISBN: (纸本)9781450305549

As soft processors are increasingly used in diverse applications, there is a need to evolve their microarchitectures in a way that suits the fpga implementation substrate. This paper compares the delay and area of a comprehensive set of processor building block circuits when implemented on custom CMOS and fpga substrates. We then use the results of these comparisons to infer how the microarchitecture of soft processors on fpgas should be different from hard processors on custom CMOS. We find that the ratios of the area required by an fpga to that of custom CMOS for different building blocks varies significantly more than the speed ratios. As area is often a key design constraint in fpga circuits, area ratios have the most impact on microarchitecture choices. Complete processor cores have area ratios of 17-27x and delay ratios of 18-26x. Building blocks that have dedicated hardware support on fpgas such as SRAMs, adders, and multipliers are particularly area-efficient (2-7x area ratio), while multiplexers and CAMs are particularly area-inefficient (> 100x area ratio), leading to cheaper ALUs, larger caches of low associativity, and more expensive bypass networks than on similar hard processors. We also find that a low delay ratio for pipeline latches (12-19x) suggests soft processors should have pipeline depths 20% greater than hard processors of similar complexity.

关键词： fpga CMOS Area Delay Soft Processor

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Reducing the Pressure on Routing Resources of fpgas with Generic Logic Chains 11

Reducing the Pressure on Routing Resources of FPGAs with Gen...

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19th Annual acm international symposium on field-programmable gate arrays

作者： Parandeh-Afshar, Hadi Zgheib, Grace Brisk, Philip Ienne, Paolo Ecole Polytech Fed Lausanne Sch Comp & Commun Sci CH-1015 Lausanne Switzerland

ISBN: (纸本)9781450305549

Routing resources in modern fpgas use 50% of the silicon real estate and are significant contributors to critical path delay and power consumption;the situation gets worse with each successive process generation, as transistors scale more effectively than wires. To cope with these challenges, fpga architects have divided wires into local and global categories and introduced fast dedicated carry chains between adjacent logic cells, which reduce routing resource usage for certain arithmetic circuits (primarily adders and subtractors). Inspired by the carry chains, we generalize the idea to connect lookup tables (LUTs) in adjacent logic cells. By exploiting the fracturable structure of LUTs in current fpga generations, we increase the utilization of the existing LUTs in the logic cell by providing new inputs along the logic chain, but without increasing the I/O bandwidth from the programmable interconnect. This allows us to increase the logic density of the configurable logic cells while reducing demand for routing resources, as long as the mapping tools are able to exploit the logic chains. Our experiments using the combinational MCNC benchmarks and comparing against an Altera Stratix-III fpga show that the introduction of logic chains reduce the average usage of local routing wires by 37%, with a 12% reduction in total wiring (local and global);this translates to improvements in dynamic power consumption of 18% in the routing network and 10% overall, while utilizing 4% fewer logic cells, on average.

关键词： fpga Logic Chain Routing Wire Dedicated Connection Generic Synthesis

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Torc: Towards an Open-Source Tool Flow 11

Torc: Towards an Open-Source Tool Flow

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19th Annual acm international symposium on field-programmable gate arrays

作者： Steiner, Neil Wood, Aaron Shojaei, Hamid Couch, Jacob Athanas, Peter French, Matthew Univ So Calif Inst Informat Sci Arlington VA 22203 USA

ISBN: (纸本)9781450305549

We present and describe Tore-Tools for Open Reconfigurable Computing an open-source infrastructure and tool set, provided entirely as C++ source code and available at http://***. Torc is suitable for custom research applications, for CAD tool development, and for architecture exploration. The Tore infrastructure can (1) read, write, and manipulate generic netlists-currently EDIF, (2) read, write, and manipulate physical netlists-currently XDL, and indirectly NCD, (3) provide exhaustive wiring and logic information for commercial devices, and (4) read, write, and manipulate bitstream packets (but not configuration frame contents). Tore furthermore provides routing and unpacking tools for full or partial designs, soon to be augmented with BLIP support, and with packing and placing tools. The architectural data for Xilinx devices is generated from non-proprietary XDLRC files, and currently supports 140 devices in 11 families: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex4, Virtex5, Virtex6, Virtex6L, Spartan3E, Spartan6, and Spartan6L. We believe that Altera architectures and designs could be similarly supported if the necessary data were available, and we have successfully used Torc internally with custom architectures.

关键词： C plus fpga place route unpack EDIT XDL XDLRC

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Proceedings of the 7th acm sigda international symposium on field-programmable gate arrays, fpga'09

Proceedings of the 7th ACM SIGDA International Symposium on ...

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7th acm sigda international symposium on field-programmable gate arrays, fpga'09

ISBN: (纸本)9781605584102

The proceedings contain 34 papers. The topics discussed include: emerging application domains - research challenges and opportunities for fpgas;towards automated ECOs in fpgas;clock power reduction for Virtex-5 fpgas;choose-your-own-adventure routing: lightweight load-time defect avoidance;towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm fpgas;a comparison of via-programmable gate array logic cell circuits;a comparison of CPUs, GPUs, fpgas, and massively parallel processor arrays for random number generation;a high-performance fpga architecture for restricted Boltzmann machines;fpga-based front-end electronics for positron emission tomography;fpga-based face detection system using Haar classifiers;a 17ps time-to-digital converter implemented in 65nm fpga technology;and fpga technology mapping with encoded libraries and staged priority cuts.

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mrfpga: A novel fpga architecture with memristor-based reconfiguration 11

mrFPGA: A novel FPGA architecture with memristor-based recon...

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Proceedings of the 2011 IEEE/acm international symposium on Nanoscale Architectures

作者： Cong, Jason Xiao, Bingjun Department of Computer Science University of California Los Angeles CA United States

ISBN: (纸本)9781457709944

In this paper, we introduce a novel fpga architecture with memristor-based reconfiguration (mrfpga). The proposed architecture is based on the existing CMOS-compatible memristor fabrication process. The programmable interconnects of mrfpga use only memristors and metal wires so that the interconnects can be fabricated over logic blocks, resulting in significant reduction of overall area and interconnect delay but without using a 3D die-stacking process. Using memristors to build up the interconnects can also provide capacitance shielding from unused routing paths and reduce interconnect delay further. Moreover we propose an improved architecture that allows adaptive buffer insertion in interconnects to achieve more speedup. Compared to the fixed buffer pattern in conventional fpgas, the positions of inserted buffers in mrfpga are optimized on demand. A complete CAD flow is provided for mrfpga, with an advanced P&R tool named mrVPR that was developed for mrfpga. The tool can deal with the novel routing structure of mrfpga, the memristor shielding effect, and the algorithm for optimal buffer insertion. We evaluate the area, performance and power consumption of mrfpga based on the 20 largest MCNC benchmark circuits. Results show that mrfpga achieves 5.18x area savings, 2.28x speedup and 1.63x power savings. Further improvement is expected with combination of 3D technologies and mrfpga. © 2011 IEEE.

关键词： field programmable gate arrays (fpga)

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