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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是751-760 订阅

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A prototype fpga for subthreshold-optimized CMOS (abstract only) 11

A prototype FPGA for subthreshold-optimized CMOS (abstract o...

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Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Peter Grossmann Miriam Leeser Northeastern University Boston MA USA

ISBN: (纸本)9781450305549

field-programmable gate arrays (fpgas) are frequently used in low power systems because they can implement the same functionality as a microprocessor in a more energy-efficient manner while still offering the benefits of low development time and cost relative to an ASIC. Similar advantages for fpgas may be found in ultra-low power applications operating at subthreshold supply voltages, where performance is sacrificed in favor of increased energy efficiency. Process technology research has demonstrated the benefits of tailoring device design to subthreshold operation. Subthreshold fpga research is only beginning, and has yet to consider use of subthreshold-optimized devices. A simplified fpga implemented in subthreshold-optimized CMOS is presented. The results obtained show that this technology provides the capability to implement an fpga suitable for ultra-low power applications consuming tens to hundreds of microwatts of average power.

关键词： fpga subthreshold

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Regular fabric for regular fpga (abstract only) 11

Regular fabric for regular FPGA (abstract only)

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Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Xun Chen Jianwen Zhu University of Toronto Toronto Canada

ISBN: (纸本)9781450305549

In the sub-wavelength regime, design for manufacturability (DFM) becomes increasingly important for field programmable gate arrays (fpgas). In this paper, we report an automated tile generation flow targeting micro-regular fabric, this flow automatically generate the basic fpga tile building block in a standard cell format and then form the whole tile with the help of commercial placing and routing tools. Using a publicly accessible, well-documented academic fpga as case study, we found that comparing to the tile generators previously reported, our generated micro-regular tile incurs less than 10% area overhead, which could be potentially recovered by process window optimization thanks to its superior printability. In addition, we demonstrate that on 45nm technology, the generated fpga tile reduces lithography induced process variation by 33%; and reduce probability of failure by 21.2%. If further overhead of 10% area can be recovered by enhanced resolution, we can achieve the variation reduction of 93.8% and reduce probability of failure by 16.2%.

关键词： fpga design for manufacturability regular design fabric layout atutomation

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Just-in-time instruction set extension - Feasibility and limitations for an fpga-based reconfigurable ASIP architecture

Just-in-time instruction set extension - Feasibility and lim...

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25th IEEE international Parallel and Distributed Processing symposium, Workshops and Phd Forum, IPDPSW 2011

作者： Grad, Mariusz Plessl, Christian Paderborn Center for Parallel Computing University of Paderborn Germany

ISBN: (纸本)9780769543857

In this paper, we study the feasibility of moving the instruction set customization process for reconfigurable ASIPs to runtime under the precondition that current fpga devices and tools are used. To this end we propose a tool flow for just-in-time ASIP customization which identifies suitable custom instructions to accelerate arbitrary binary applications that execute on a virtual machine. The tool flow targets our previously introduced Woolcano reconfigurable ASIP architecture, which augments the PowerPC core in a Xilinx Virtex 4FX CPU with runtime reconfigurable instructions. We evaluate the tool flow with a comprehensive set of applications from the SPEC2006, SPEC2000, MiBench, and SciMark2 benchmark suites and compare the speedups that can be achieved with the overhead of the complete ASIP specialization process. We show that an average speedup of 5× can be achieved for benchmarks from the embedded computing domain. The overhead of custom instruction identification and hardware generation for these benchmarks is less than 50 minutes and will be compensated if the applications execute for more than 2 hours. Finally, we evaluate caching strategies to reduce the time until this break even point is reached. © 2011 IEEE.

关键词： field programmable gate arrays (fpga)

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Variation tolerant asynchronous fpga (abstract only) 11

Variation tolerant asynchronous FPGA (abstract only)

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Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Hock Soon Low DeLong Shang Fei Xia Alex Yakovlev Newcastle University Newcastle upon Tyne United Kingdom

ISBN: (纸本)9781450305549

This paper describes the realization of an interconnect Delay Insensitive (DI) fpga architecture with distributed asynchronous control. This architecture maintains the basic block structure of traditional fpgas allowing the potential use of existing fpga design tools in block design. This asynchronous fpga architecture is mainly aimed at tolerating the unpredictable delay variations caused by process and environment variations in current and future VLSI technology nodes and also targets low power operations, including modes such as dynamic voltage scaling and variable Vdd, as in applications featuring energy harvesting. This is achieved by making the longer inter-block interconnects DI, keeping the computational logic single-rail, and removing global clocks.

关键词： variability distributed control process variation asynchronous fpga

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Memory based computing: reshaping the fine-grained logic in a reconfigurable framework (abstract only) 11

Memory based computing: reshaping the fine-grained logic in ...

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Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Somnath Paul Swarup Bhunia Case Western Reserve University Cleveland OH USA

ISBN: (纸本)9781450305549

Conventional field programmable gate Array (fpga) architectures leverage on the purely spatial computing model where a design is realized in the form of a small multiple-input single-output lookup tables (LUTs) connected through programmable interconnect switches. However, such a model incorporates an elaborate programmable interconnect network which becomes a major performance bottleneck and leads to poor scalability across process technology nodes. In this paper we evaluate an alternative two-dimensional static random access memory (SRAM) array based reconfigurable computing fabric, referred to as "Memory Based Computing" (MBC) that departs from a purely spatial architecture by advocating multi-cycle evaluation at each computational element. Within a computational element, it uses a dense two-dimensional SRAM array to map large multi-input multi-output functions as LUT and evaluate them in time-multiplexed topological fashion. Multi-cycle execution at each computing node is accomplished using a local interconnect architecture. The proposed framework substantially reduces the requirement for global interconnects by folding computational resources onto a single computational element. We explore the design space for MBC to optimize the major design parameters and compare the performance, power dissipation and energy-delay product for benchmark applications between MBC and conventional SRAM-based fpga. Simulation results show that compared to a clustered fpga model, the proposed framework achieves 57% improvement in performance, 30% improvement in Energy Delay Product (EDP) and 10% improvement in technological scalability of performance for standard benchmark circuits. Finally, we validate the functionality of MBC framework and timing of different operations by mapping several small applications on a Cyclone III fpga platform from Altera.

关键词： memory based computation field programmable gate array (fpga) recongurable hardware

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Fault modeling and characteristics of SRAM-based fpgas (abstract only) 11

Fault modeling and characteristics of SRAM-based FPGAs (abst...

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Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Naifeng Jing Ju-Yueh Lee Chun Zhang Jiarong Tong Zhigang Mao Lei He Shanghai Jiao Tong University Shanghai China University of California Los Angeles Los Angeles CA USA Fudan University Shanghai China

ISBN: (纸本)9781450305549

The reliability of SRAM-based field programmable gate Array (fpga) is susceptible to Single Event Upset (SEU) fault. To investigate the fault impact, particular the fault in interconnects on fpga functionality, this paper proposes a SEU fault analysis framework by evaluating the fault with a unified metric. This metric, termed as criticality, quantifies the sensitivity of fpga functional failure to the SEU fault on logical and interconnect configuration bits. Considering the post layout information, our framework can characterize the SEU fault with respect to different fpga architectures and CAD algorithms, such that the sensitivity of fpga functional failure can be investigated in detail during design phase. The experiment result quantitatively shows that the configuration bits in interconnects dominate those in LUTs, several times both in bit number and criticality contribution. The ratio of their criticalities is even higher when LUT input size increases from 4 to 6. The higher criticality of interconnects than their LUT counterpart is due to their natural sensitivity to functional failure instead of their majority of bits. In addition, it is also shown that, among the three common types of switch boxes, the Subset switch box is less fault tolerant than Wilton and Universal.

关键词： fault tolerance seu fpga reliability interconnects

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fpga-based nand flash memory error characterization and solid-state drive prototyping platform (abstract only) 11

FPGA-based nand flash memory error characterization and soli...

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Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Yu Cai Erich Haratsch Mark McCartney Mudit Bhargava Ken Mai Carnegie Mellon University Pittsburgh USA LSI Company Allentown PA USA

ISBN: (纸本)9781450305549

NAND Flash memory has been widely used for data storage due to its high density, high throughput, low cost, and low power. However, as the storage cells become smaller and with more bits programmed per cell, they are expected to suffer from reduced reliability and limited endurance. Wear-leveling and signal processing can significantly improve both reliability and endurance. However, finding optimal algorithms would require a quick and accurate characterization of Flash memory providing an insight into the error patterns. To this end, we have designed and implemented an fpga-based framework for quick, accurate, and comprehensive characterization of Flash memories to allow efficient algorithm explorations.

关键词： nand flash fpga flash controller solid state drive

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fpga placement by graph isomorphism (abstract only) 11

FPGA placement by graph isomorphism (abstract only)

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Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Hossein Omidian Savarbaghi Kia Bazargan Islamic Azad University Tehran Iran University of Minnesota Minneapolise MN USA

ISBN: (纸本)9781450305549

fpga placement and routing are still challenging problems. Given the increased diversity of logic and routing resources on fpga chips, it seems appropriate to tackle the placement problem as a mapping between the nodes and edges in a circuit graph to compatible resources in the architecture graph. We explore utilizing graph isomorphism algorithms to perform fpga placement. We use a hierarchical approach in which the circuit and architecture graphs are simultaneously clustered to reduce the size of the search space, and then a novel reductive graph product method is used to solve the isomorphism problem. The graph product algorithm is called reductive as it eliminates a linear number of candidates at every step of the search process, reducing the number of candidate nodes by approximately 1/3. Compared to the annealing-based placement tool VPR 5.0, we achieve approximately 40% improvement in placement runtime, while improving the critical path delay by about 7% and wire length by 5%, while demanding 1.3% more channels on average.

关键词： placement clustering graph isomorphism graph product

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Low power interconnect design for fpgas with bidirectional wiring using nanocrystal floating gate devices (abstract only) 11

Low power interconnect design for fpgas with bidirectional w...

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Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Daniel Schinke Wallace Shep Pitts Neil Di Spigna Paul Franzon North Carolina State University Raleigh NC USA

ISBN: (纸本)9781450305549

New architectures for the switch box and connection block are proposed for use in an energy efficient field programmable gate array (fpga) with bidirectional wiring. Power-hungry SRAMs are replaced by non-volatile nanocrystal floating gate (NCFG) devices that retain their state while the system power is off and do not need to be configured at boot up. The NCFG-based fpga is benchmarked against both a traditional bidirectional and a modern unidirectional SRAM-based fpga using a 32-tap FIR Filter designed in HSPICE based on predictive BSIM4.0 CMOS with 45nm gate length technology and a previously developed physical model of the NCFG device. Compared to the traditional bidirectional and the modern unidirectional SRAM-based interconnect the total gate area is reduced by 87% and 63%, respectively. Simulations demonstrate a reduction of 58% in static and 34% in dynamic power consumption compared to the traditional bidirectional SRAM-based fpga while the signal propagation delay through a switch box is decreased by 28%. When compared to the modern unidirectional SRAM-based fpga the proposed design has roughly comparable power consumption but the circuit complexity is greatly reduced as a result of doubling the available routing channels. Alternatively the number of the routing channels may be reduced to save area and power whereas the complexity remains similar. The potential benefits from choosing the proposed design can be summarized as small area, low power consumption, high speed and high functionality, which typically trade off and cannot be achieved by the SRAM-based counterparts simultaneously. Compared to previous designs that use continuous floating gate devices in fpgas, the approach described in this work requires less overhead, lower voltages, and offers improved reliability.

关键词： high speed fpga floating gate switch box nanocrystal connection block low power bidirectional wiring

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A chip-level path-delay-distribution based Dual-VDD method for low power fpga (abstract only) 11

A chip-level path-delay-distribution based Dual-VDD method f...

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Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Jianfeng Zhu Dong Wu Yaru Yan Xiao Yu Hu He Liyang Pan Tsinghua University Beijing China

ISBN: (纸本)9781450305549

Dual-VDD fpga architecture has been proposed to reduce the fpga's power consumption, where a low VDD (VDDL) is assigned to non-critical resources and unused resources are power-gated. In this paper, a path-delay-distribution (PDD) based design method of supply voltage in dual-VDD fpga is developed, which gives an estimated optimal VDD solution for the required applications. Meanwhile, an improved tree-based VDD assignment algorithm is accordingly designed. Thus chip-level optimization of dual-VDD fpga is achieved on the chosen granularity with the power consumption minimized. Based on MCNC benchmark circuits at 90nm technology node, our experimental result shows that: the power reduction rate depends on VDDL level; the design method proposed in this work gives the optimal one automatically. This design method could be utilized to guide the fpga automatic design, saving the time to search for the system's optimal supply voltage, and the proposed assignment algorithm is more efficient in dynamic power reduction.

关键词： path delay distribution fpga dual-vdd

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