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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是761-770 订阅

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fpga-based fine-grain parallel computing (abstract only) 11

FPGA-based fine-grain parallel computing (abstract only)

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Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Andrew W. Hill Andrea Di Blas Richard Hughey University of California Santa Cruz Santa Cruz CA USA

ISBN: (纸本)9781450305549

fpgas are increasing in computing power at a significant rate while the non-recurring engineering costs and time-to-market remain significant lower than those for application-specific integrated circuits (ASICs), encouraging fpgas to be used in areas previous dominated by ASICs. In this study, we examine the appropriateness of fpgas for high-performance, low-volume prodution parallel computing by mapping an existing ASIC-based massively parallel single-instruction, multiple data (SIMD) computer, the UCSC Kestrel, to a variety of fpgas. The design has a raw peak performance of over 187 billion 8-bit operations per second (OPS), 48 times faster than the original ASIC-based Kestrel, using a Xilinx Virtex-6, and a cost efficiency of up to 81 MOPS/$ using a Xilinx Spartan-3. We also show that we can implement the entire original Kestrel (512 processing elements) as a system on a single programmable chip.

关键词： system on a programmable chip simd parallel computing

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A streaming fpga implementation of a steerable filter for real-time applications (abstract only) 11

A streaming FPGA implementation of a steerable filter for re...

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Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Srinidhi Kestur Dharav Dantara Vijaykrishnan Narayanan The Pennsylvania State University University Park PA USA

ISBN: (纸本)9781450305549

Oriented filters are used in many early vision and image processing tasks for feature extraction at arbitrary orientations. Steerable filters are a class of filters in which a filter of arbitrary orientation is synthesized as a linear combination of a set of basis filters. In this work, we describe a streaming implementation of a steerable filter on fpgas, which includes a two-dimensional convolution filter and a modulator for modulation by a set of oriented sine waves. We present a highly configurable streaming 2D convolution implementation and a novel separable look-up-table based implementation of the modulation step. This steerable filter has been extended to multiple resolutions to realize a steerable pyramid filter. Experimental results on a Virtex6 fpga show that the steerable pyramid filter provides up to 14X and 21X speedups over related fpga and CPU implementations respectively. This work was supported in part by a grant from NSF 0916887 and DARPA Neovision2 programs.

关键词： pyramid filter ml605 gabor filter fpga implementation convolution steerable filter modulation

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Resolving implicit barrier synchronizations in fpga HLS (abstract only) 11

Resolving implicit barrier synchronizations in FPGA HLS (abs...

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Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Jason Cong Yi Zou University of California Los Angeles Los Angeles CA USA

ISBN: (纸本)9781450305549

Existing C-to-fpga high-level synthesis (HLS) tools are good at exploiting instruction-level and loop-level parallelism, but not efficient at exploiting task-level parallelism (or requires extensive manual re-write). In this paper, we present an automated flow and architecture template to map task-level data-model (coarse-grain task graphs) onto fpgas. We automatically generate multiple communicating FSMDs (finite-state machine with datapath) based on the architecture template to manage the required synchronization and communication. The key architectural components in our approach include a progress table that traces task execution, an automatic memory duplication scheme that enables a larger parallelism and provides isolation between different tasks, and a memory lifetime analysis and reuse scheme to reduce the on-chip memory consumption. Through data-flow driven execution, the presented flow can reduce the total latency by 30%, with moderate area overhead, when compared with the RTL implementation using a single hierarchical FSMD generated by a state-of-art HLS tool.

关键词： fpga template barrier

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The role of fpgas in a converged future with heterogeneous programmable processors: pre-conference workshop 11

The role of FPGAs in a converged future with heterogeneous p...

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Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Jonathan Rose Guy Lemieux University of Toronto Toronto ON Canada University of British Columbia Vancouver BC Canada

ISBN: (纸本)9781450305549

The battle of fixed function devices vs. programmable devices has been won by the programmables. The question facing us now is to determine what kinds of programmability to place on next generation systems/devices. Research and development on many applications has shown that different kinds of hardware and software programmability succeed for different application classes: powerful, singlethread-optimized CPUs continue to do very well for many applications; the General Purpose GPU is carving a niche in high throughput, parallel floating point codes in addition to its home turf of graphics; the fpga is particularly good at variable bit-size computations and data steering, as well as parallel distributed control of networks. Future systems may well need all three types of these types of engines, and perhaps interesting mixtures of them. This is particularly true when we deal with the combined goals of optimizing cost, performance and *** this workshop, we will look to the future of the fpga within these types of 'converged' programmable computing engines, and reflectively ask ourselves: What role can the fpga play? What future applications in areas such as networking, mobile, and artificial intelligence can be driven by fpgas? How do fpgas fit into the architecture realm of CPUs, general purpose GPUs, and DSPs? How should the designer/programme express their intent in the most effective way possible? What are the requirements for a compilation and optimization environment that allow fpgas to intermix within a heterogeneous and converged future?The intent of this workshop is to open a discussion on these questions. There will be a series of short, invited talks interspersed with free and open discussion.

关键词： heterogeneity reconfigurable computing high level programming models fpga heterogeneous computing systems signal processing dsp

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A comparison of fpgas, GPUS and CPUS for Smith-Waterman algorithm (abstract only) 11

A comparison of FPGAs, GPUS and CPUS for Smith-Waterman algo...

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Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Yoshiki Yamaguchi Kuen Hung Tsoi Wayne Luk University of Tsukuba Tsukuba Japan Imperial College London London United Kingdom

ISBN: (纸本)9781450305549

The Smith-Waterman algorithm is a key technique for comparing genetic sequences. This paper presents a comprehensive study of a systolic design for Smith-Waterman algorithm. It is parameterized in terms of the sequence length, the amount of parallelism, and the number of fpgas. Two methods of organizing the parallelism, the line-based and the lattice-based methods, are introduced. Our analytical treatment reveals how these two methods perform relative to peak performance when the level of parallelism varies. A novel systolic design is then described, showing how the parametric description can be effectively implemented, with specific focus on enhancing parallelism and on optimizing the total size of memory and circuits; in particular, we develop efficient realizations for compressing score matrices and for reducing affine gap cost functions. Promising results have been achieved showing, for example, a single XC5VLX330 fpga at 131MHz can be three times faster than a platform with two NVIDIA GTX295 at 1242MHz.

关键词： fpga gpgpu sequence alignment performance comparison smith-waterman algorithm

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Using many-core architectural templates for fpga-based computing (abstract only) 11

Using many-core architectural templates for FPGA-based compu...

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Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Mingjie Lin Shaoyi Cheng John Wawrzynek University of California at Berkeley Berkeley CA USA

ISBN: (纸本)9781450305549

Truly unleashing the computing potential of fpgas, as well as widening their applicability, demands alleviating cumbersome HDL programming and relieving laborious manual optimization. Towards this end, we propose a Many-core Approach to Reconfigurable Computing (MARC) that enables efficient high-performance computing for applications expressed with imperative programming languages such as C/C++ without constructing fpga computing machines from scratch when targeting various applications within the same or similar problem domains. A MARC system achieves high computing performance by leveraging a many-core architectural template, sophisticated logic synthesizing techniques, and state-of-art compiler optimization technology. In addition, MARC exploits abundant special fpga resources such as distributed block memories and DSP blocks to implement complete single-chip high efficiency many-core microarchitectures. The key benefits of MARC include (i) allowing programmers to easily express parallelism through a high-level programming language, (ii) supporting coarse-grain multithreading and dataflow-style fine-grain threading while permitting bit-level resource control, and (iii) greatly reducing the effort required to re-purpose the hardware system for different algorithms or different applications.

关键词： computing fpga template many-core

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Microblaze: an application-independent fpga-based profiler (abstract only) 11

Microblaze: an application-independent fpga-based profiler (...

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Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Fadi Obeidat Robert Klenke Virginia Commonwealth University Richmond VA USA

ISBN: (纸本)9781450305549

Monitoring the functional behavior of an application is an important capability that assists in exploring the performance of a target application against different SW/HW implementations. Recently, there have been efforts to exploit the ability to trace the internal signals of the soft-core processors for developing fpga-based profiling tools to monitor programs running on these processors. However, these previously developed techniques are application-dependent, i.e., they require the designer either to edit the HDL code or the application code to obtain the desired trace information when targeting new applications. In this research, we propose an application-independent profiling technique using the MicroBlaze/fpga platform where profiling library or user-defined functions can be achieved by tracing the unique instruction flow that distinguishes functions from each other rather than monitoring the program counter value (the addresses of the functions). Hence, modifying the application code or targeting new application does not require reconfiguring the fpga or modifying the application code for targeting the same functions. This technique can be used to analyze the target application at the source code level, observing the dominant operations and demanded resources that characterize the system behavior. In addition, this technique can assist in selecting the appropriate processor architecture for a given application by considering MicroBlaze as a reference architecture from which the functional behavior of the target application can be mapped to the performance of other architectures.

关键词： performance modeling hw/sw codesign fpga-based profiling

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On timing yield improvement for fpga designs using architectural symmetry (abstract only) 11

On timing yield improvement for FPGA designs using architect...

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Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Haile Yu Qiang Xu Philip H.W. Leong The Chinese University of Hong Kong Hong Kong Hong Kong The University of Sydney Sydney Australia

ISBN: (纸本)9781450305549

As semiconductor manufacturing technology continues towards reduced feature sizes, timing yield will degrade due to increased process variation. Traditional variation aware design (VAD) methodologies address this problem by using chipwise placement and routing optimizations given the variation distribution is obtained. However, it is very time-consuming to do chipwise variation characterization and optimization. Therefore, this work proposes the use of symmetry in fpga architectures so that a large range of timing-equivalent configurations can be derived from a single initial implementation by configuration rotation and flipping, allowing the application of post-silicon tuning to mitigate the effects of process variation. Additionally, logic element swaps further improve timing performance. An fpga design methodology is presented which combines configuration-level redundancy and fine-grained design tuning. The proposed methodology does not need variation characterization and customized placement and routing for each individual fpga. Compared to other variation aware design methods, it is more cost-efficient in terms of run-time, especially for design implementation on a large amount of fpgas. Twenty MCNC benchmark circuits in different process technologies were used to show that the proposed method is effective in improving yield and timing in the presence of process variation.

关键词： process variation yield fpga symmetrical architecture

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High level synthesis for fpgas applied to a sphere decoder channel preprocessor (abstract only) 11

High level synthesis for FPGAs applied to a sphere decoder c...

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Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Sven van Haastregt Stephen Neuendorffer Kees Vissers Bart Kienhuis Leiden University Leiden Netherlands Xilinx Research Labs San Jose CA USA

ISBN: (纸本)9781450305549

During the 1990s, High Level Synthesis (HLS) slowly started emerging to allow designers to cope with the ever-increasing complexity of digital signal processing systems such as wireless receivers. Only recently, a new generation of high-quality commercial HLS tools capable of generating decent RTL architectures from algorithmic-style code has become available. Although these tools are now starting to be adopted for actual designs, detailed experiences and results for these tools in significant designs is still lacking. In this work we have analyzed the design process of a significant portion of a wireless communication application using AutoESL's AutoPilot HLS tool. We target a Xilinx Virtex-5 fpga device and a clock frequency of 225 MHz. We have compared our HLS implementation to a reference implementation obtained using manual RTL design methods. We found that our HLS implementation is competitive to this reference implementation in terms of throughput and resource cost. The time needed to obtain a first HLS implementation matching throughput and resource cost aspects of the reference implementation is similar to the design time of the reference implementation. After obtaining a first HLS implementation, we were able to explore and implement different application architectures with HLS in only a couple of hours, thereby gaining significant savings in design time over manual RTL design, where architectural exploration may take weeks.

关键词： fpga high level synthesis sphere decoder

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Should the academic community launch an open-source fpga device and tools effort?: evening panel 11

Should the academic community launch an open-source FPGA dev...

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Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： John Wawrzynek University of California at Berkeley Berkeley CA USA

ISBN: (纸本)9781450305549

For years, many academic researchers in reconfigurable computing have been frustrated by their reliance on commercial fpgas and tools. Commercial fpgas have highly complex micro-architectures, come with undocumented binary interfaces, have no compatibility between generations, and come with difficult to use proprietary place and route tools. The fpga vendors are making the right moves for serving their commercial customer base, but it seems at times these moves are in conflict with the needs of the academic research *** problems make it difficult for academics to teach fpga design and to participate in relevant research related to fpgas. Complex fpga fabrics and undocumented proprietary interfaces make it nearly impossible to build new tools to target actual commercial devices. University researchers are now hesitant to participate in fpga architecture research because the level of complexity of fpgas is beyond what is possible to implement in an academic setting. Reconfigurable computing application developers are at the mercy of complex fpga devices and closed-source place and route tools - not optimized for computing *** argue that the time is right for academia to break away and create an open source fpga device. Such an effort would enable university researchers to take an active role in architecture design, and promote an open source community effort in developing and advancing the state of the art of tools.A similar situation existed in the early 80's surrounding processor design. As a result of competition among the big computer companies, microprocessor designs had evolved from very simple beginnings to highly complex architectures and equally complex compilers. Universities were largely on the sidelines, as they couldn't compete at the level of industrial designs of the day. "RISC" changed all that. By adopting simple architectures, universities were once again able to actually design and implement their own processors and to inno

关键词： open source reconfigurable computing fpga signal processing design tools high level programming models dsp

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