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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是781-790 订阅

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Combining Multicore and Reconfigurable Instruction Set Extensions 10

Combining Multicore and Reconfigurable Instruction Set Exten...

引用

18th acm international symposium on field-programmable gate arrays

作者： Chen, Zhimin Pittman, Richard N. Forin, Alessandro Virginia Tech ECE Dept Blacksburg VA 24060 USA

ISBN: (纸本)9781605589114

The shift to multi-core processors presents a number of opportunities and challenges to different research fields, including the field of fpga applications. This paper investigates the advantages of combining multi-core processors and reconfigurable instruction set extensions. Both our analysis and the experimental results show that these two approaches exploit different levels of parallelism. Using a case study on the Floyd-Warshall algorithm, we demonstrate that the multi-core architecture and the reconfigurable instruction set extensions complement each other. By combining these two methods together we find a win-win solution, which gives us a more efficient implementation with higher performance.

关键词： fpga Multi-core Reconfigurable Instruction Set Extensions Extensible Microprocessors Embedded

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Accelerating Monte Carlo based SSTA Using fpga 10

Accelerating Monte Carlo based SSTA Using FPGA

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18th acm international symposium on field-programmable gate arrays

作者： Cong, Jason Gururaj, Karthik Jiang, Wei Liu, Bin Minkovich, Kirill Yuan, Bo Zou, Yi Univ Calif Los Angeles Dept Comp Sci Los Angeles CA 90095 USA

ISBN: (纸本)9781605589114

Monte Carlo based SSTA serves as the golden standard against alternative SSTA algorithms, but it is seldom used in practice due to its high computation time. In this paper, we accelerate Monte Carlo based SSTA using the fpga platform. A simple dataflow pipeline technique will not work well due to the excessive usage of fpga logic slices. We leverage the recently proposed pattern matching method to identify common circuit structures, and further use a mathematical programming based formulation to explore the trade-off between performance and logic slices consumption. The proposed design provides two orders of magnitude speedup compared to the CPU-based implementation.

关键词： fpga Monte Carlo SSTA

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fpga Power Reduction by Guarded Evaluation 10

FPGA Power Reduction by Guarded Evaluation

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18th acm international symposium on field-programmable gate arrays

作者： Anderson, Jason H. Ravishankar, Chirag Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 1A1 Canada

ISBN: (纸本)9781605589114

Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times during circuit operation, thereby reducing switching activity and lowering dynamic power. The concept is rooted in the property that under certain conditions, some signals within digital designs are not "observable" at design outputs, making the circuitry that generates such signals a candidate for guarding. Guarded evaluation has been demonstrated successfully for custom ASICs;in this paper, we apply the technique to fpgas. In ASICs, guarded evaluation entails adding additional hardware to the design, increasing silicon area and cost. Here, we apply the technique in a way that imposes minimal area overhead by leveraging existing unused circuitry within the fpga. The primary challenge in guarded evaluation is in determining the specific conditions under which a sub-circuit's inputs can be held constant without impacting the larger circuit's functional correctness. We propose a simple solution to this problem based on discovering "non-inverting paths" in the circuit's AND-inverter graph representation. Experimental results show that guarded evaluation can reduce switching activity by 22%, on average, and can reduce power consumption in the fpga interconnect by 14%.

关键词： field-programmable gate arrays fpgas power optimization low-power design logic synthesis technology mapping

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The Impact of Interconnect Architecture on Via-Programmed Structured ASICs (VPSAs) 10

The Impact of Interconnect Architecture on Via-Programmed St...

引用

18th acm international symposium on field-programmable gate arrays

作者： Ahmed, Usman Lemieux, Guy G. F. Wilton, Steven J. E. Univ British Columbia Dept Elect & Comp Engn Vancouver BC V5Z 1M9 Canada

ISBN: (纸本)9781605589114

In this paper, we evaluate the performance of an fpga-like interconnect fabric for structured ASICs which is based upon fixed metal and programmable vias. We call this type of device a via-programmed structured ASIC or VPSA. We look at two different types of VPSA routing fabrics: one uses jumper wiring and the other uses crossover wiring. The performance of these fabrics is compared against an ASIC-like interconnect fabric, otherwise known as a metal-programmed structured ASIC or MPSA, which can be configured by customizing metal and via layers. We study the impact of these routing fabrics on cost, area, power and delay metrics. The results for different fabrics span a wide range, suggesting the routing architecture plays a very important role in their overall performance and it should be thoroughly researched.

关键词： Structured ASICs Via programmable Fabric

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Building a Faster Boolean Matcher Using Bloom Filter 10

Building a Faster Boolean Matcher Using Bloom Filter

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18th acm international symposium on field-programmable gate arrays

作者： Zhang, Chun Hu, Yu Wang, Lingli He, Lei Tong, Jiarong Fudan Univ State Key Lab ASIC & Syst Shanghai Peoples R China

ISBN: (纸本)9781605589114

Boolean matching is one of the most important fundamental algorithms in fpga synthesis and architecture evaluations. However, existing Boolean matchers for fpgas, even with numerous improvements, are still not scalable to complex PLBs and large circuits. This paper aims to improve the efficiency of Boolean matching using look-up tables implemented by Bloom filters, which can store terabyte-lookup tables with a desktop PC. The key improvement is to efficiently prune a large set of non-implementable functions use the Bloom filter. Using the area-oriented re-synthesis as an application, the experiments on a broad selection of benchmark sets show that the re-synthesis with our improved Boolean matcher is 18X faster than the one with an optimized SAT-based Boolean matcher, while preserving the quality of the re-synthesizer.

关键词： fpga Boolean Matching Bloom Filter SAT Re-synthesis

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Scalable Network Virtualization Using fpgas 10

Scalable Network Virtualization Using FPGAs

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18th acm international symposium on field-programmable gate arrays

作者： Unnikrishnan, Deepak Vadlamani, Ramakrishna Liao, Yong Dwaraki, Abhishek Crenne, Jeremie Gao, Lixin Tessier, Russell Univ Massachusetts Amherst MA 01003 USA

ISBN: (纸本)9781605589114

Recent virtual network implementations have shown the capability to implement multiple network data planes using a shared hardware substrate. In this project, a new scalable virtual networking data plane is demonstrated which combines the performance efficiency of fpga hardware with the flexibility of software running on a commodity PC. Multiple virtual router data planes are implemented using a Vir:ex II-based Netfpga card to accommodate virtual networks requiring superior packet forwarding performance. Numerous additional data planes for virtual networks which require less bandwidth and slower forwarding speeds are implemented on a commodity PC server via software routers. Through experimentation, we determine that a throughput improvement of up to two orders of magnitude can be achieved for fpga-based virtual routers versus a software-based virtual router implementation. Dynamic fpga reconfiguration is supported to adapt to changing networking needs. System scalability is demonstrated for up to 15 virtual routers.

关键词： Virtual networks fpga

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A 3D-Audio Reconfigurable Processor 10

A 3D-Audio Reconfigurable Processor

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18th acm international symposium on field-programmable gate arrays

作者： Theodoropoulos, Dimitris Kuzmanov, Georgi Gaydadjiev, Georgi Delft Univ Technol Dept Elect Engn Comp Engn Lab NL-2600 GA Delft Netherlands

ISBN: (纸本)9781605589114

Various multimedia communication systems based on 3D-Audio algorithms have been proposed by researchers from the acoustic data processing domain. However, all systems reported in the literature follow a PC-based approach that introduces processing bottlenecks and excessive power consumption. In order to alleviate these problems, we propose a reconfigurable 3D-Audio processor that can record and render sound sources concurrently. Audio recording and rendering are performed by two hardware accelerators exploiting the beamforming and the Wave field Synthesis algorithms. The theoretical scalability of the proposed processor is explored with respect to systems consisting of different microphone and loudspeaker arrays configurations. A working fpga prototype is compared against a software implementation on a Core2 Duo system. Results suggest that the proposed reconfigurable hardware solution can process data up to 2.4x faster than the software approach, while power consumption is approximately 7 Watts according to the Xilinx XPower report.

关键词： 3D-Audio Wave field Synthesis Beamforming Reconfigurable Computing Communication Systems

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Efficient Multi-Ported Memories for fpgas 10

Efficient Multi-Ported Memories for FPGAs

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18th acm international symposium on field-programmable gate arrays

作者： LaForest, Charles Eric Steffan, J. Gregory Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 1A1 Canada

ISBN: (纸本)9781605589114

Multi-ported memories are challenging to implement with fpgas since the provided block RAM;typically have only two ports. We present a thorough exploration of the design space of fpga-based soft multi-ported memories by evaluating conventional solutions to this problem, and introduce a new design that efficiently combines block RAMs into multi-ported memories with arbitrary numbers of read and write ports and true random access to any memory location, while achieving significantly higher operating frequencies than conventional approaches. For example we build a 256-location, 32-bit, 12-ported (4-write, 8-read) memory that operates at 281 MHz on Altera Stratix III fpgas while consuming an area equivalent to 3679 ALMs: a 43% speed improvement and 84% area reduction over a pure ALM implementation, and a 61% speed improvement over a pure "multipumped" implementation, although the pure multipumped implementation is 7.2x smaller.

关键词： fpga memory multi-port parallel

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Variation-Aware Placement for fpgas with Multi-cycle Statistical Timing Analysis 10

Variation-Aware Placement for FPGAs with Multi-cycle Statist...

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18th acm international symposium on field-programmable gate arrays

作者： Lucas, Gregory Dong, Chen Chen, Deming Univ Illinois Dept Elect & Comp Engn Urbana IL USA

ISBN: (纸本)9781605589114

Deep submicron processes have allowed fpgas to grow in complexity and speed. However, such technology scaling has caused fpgas to become more susceptible to the effects of process variation. In order to obtain sufficient yield values, it is now necessary to consider process variation during physical design. It is common for fpgas to contain designs with multi-cycle paths to help increase the performance, but current SSTA techniques cannot support this type of timing constraint. We propose an extension to block-based SSTA to consider multi-cycle paths. We then use this new SSTA to optimize fpga placement with our tool VMC-Place for designs with multi-cycle paths. Our experimental results show our multi-cycle SSTA is accurate to 0.59% for the mean and 0.0024% for the standard deviation. Our results also show that VMC-Place is able to improve the clock period by 9.42% or the performance yield by 68.51% compared to a single-cycle variation-aware placer.

关键词： ssta fpga multi-cycle statistical static timing analysis variation-aware placement

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Degradation in fpgas: Measurement and Modelling 10

Degradation in FPGAs: Measurement and Modelling

引用

18th acm international symposium on field-programmable gate arrays

作者： Stott, Edward A. Wong, Justin S. J. Sedcole, Pete Cheung, Peter Y. K. Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn London England

ISBN: (纸本)9781605589114

Progress in VLSI technology is driven by increasing circuit density through process scaling, but with shrinking geometry conies an increasing threat to reliability. fpgas are uniquely placed to tackle degradation and faults due to their regular structure and ability to reconfigure, giving them the potential to implement system-level reliability enhancements. To assess the scale of the challenge, a method for measuring and monitoring degradation in an fpga was developed and used to conduct an accelerated life test on a modern device. This revealed a clear, gradual degradation in timing performance that matches the expected effects of Negative-Bias Temperature Instability and Hot Carrier Injection, two of the most important VLSI degradation mechanisms. Further insight into ageing phenomena was gained using modelling - showing how degradation in a typical LUT would be affected by different usage conditions, and predicting in detail the effects on circuit behaviour.

关键词： fpga Self Test

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