The negotiation-based routing paradigm has been used successfully in a number of fpga routers. In this paper, we report several new findings related to the negotiation-based routing paradigm. We examine in-depth the c...
详细信息
The negotiation-based routing paradigm has been used successfully in a number of fpga routers. In this paper, we report several new findings related to the negotiation-based routing paradigm. We examine in-depth the convergence of the negotiation-based routing algorithm. We illustrate that the negotiation-based algorithm can be parallelized. Finally, we demonstrate that a negotiation-based parallel fpga router can perform well in terms of delay and speedup with practical fpga circuits.
As fieldprogrammablegatearrays (fpgas) have advanced, the capabilities and variety of embedded resources have increased. In the last decade, signal processing has become one of the main driving applications for FPG...
详细信息
ISBN:
(纸本)9781450311557
As fieldprogrammablegatearrays (fpgas) have advanced, the capabilities and variety of embedded resources have increased. In the last decade, signal processing has become one of the main driving applications for fpga adoption, so fpga vendors tailored their architectures to such applications. The resulting embedded digital signal processing (DSP) blocks have now advanced to the point of supporting a wide range of operations. In this paper, we explore how these DSP blocks can be applied to general computation. We show that the DSP48E1 blocks in Xilinx Virtex-6 devices support a wide range of standard processor instructions which can be designed into the core of a basic processor with minimal additional logic usage.
In this paper we propose new techniques for thermal and power characterization of fieldprogrammablegatearrays (fpgas) using infrared imaging techniques. For thermal characterization, we capture the thermal emission...
详细信息
ISBN:
(纸本)9781450305549
In this paper we propose new techniques for thermal and power characterization of fieldprogrammablegatearrays (fpgas) using infrared imaging techniques. For thermal characterization, we capture the thermal emissions from the backside of an fpga chip during operation. We analyze the captured emissions and quantify the extent of thermal gradients and hot spots in fpgas. Given that fpgas are fabricated with no knowledge of the potential field designs, we propose soft sensing techniques that can combine the measurements of hard sensors to accurately estimate the temperatures where no sensors are embedded. For power characterization, we propose algorithmic techniques to invert the thermal emissions from fpgas into spatial power estimates. We demonstrate how this technique can be used to produce spatial power maps of soft processors during operation.
This paper describes a bus mastering implementation of the PCI Express protocol using a Xilinx fpga. While the theoretical peak performance of PCI Express is quite high, attaining that performance is a complex endeavo...
详细信息
ISBN:
(纸本)9781605584102
This paper describes a bus mastering implementation of the PCI Express protocol using a Xilinx fpga. While the theoretical peak performance of PCI Express is quite high, attaining that performance is a complex endeavor on top of an already complex protocol. The implementation is described and its performance is analyzed. Source code is offered for free download via the web. Copyright 2009 acm.
In this paper we present new technology mapping algorithms for use in a programmable logic device (PLD) that contains both lookup tables (LUTs) and PLA-like blocks. The technology mapping algorithms partially collapse...
详细信息
ISBN:
(纸本)9781581131932
In this paper we present new technology mapping algorithms for use in a programmable logic device (PLD) that contains both lookup tables (LUTs) and PLA-like blocks. The technology mapping algorithms partially collapse circuits to reduce either area or depth, and pack the circuits into a minimum number of LUTs and PLA-like blocks. Since no other technology mapping algorithm for this problem has been previously published, we cannot compare our approach to others. Instead, to illustrate the importance of this problem we use our algorithms to investigate the benefits provided by a PLD architecture with both LUTs and PLA-like blocks compared to a traditional LUT-based fpga. The experimental results indicate that our mixed PLD architecture is more area-efficient than LUT-based fpgas by up to 29%, or more depth-efficient by up to 75%.
The fieldprogrammable Counter Array (FPCA) was introduced to improve fpga performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an fpga. To exploit the FPCA, a circuit i...
详细信息
ISBN:
(纸本)9781595939340
The fieldprogrammable Counter Array (FPCA) was introduced to improve fpga performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an fpga. To exploit the FPCA, a circuit is transformed by merging disparate addition and multiplication operations into large multi-input addition operations, which are synthesized as compressor trees on the FPCA;the remaining portion of the circuit is synthesized on the fpga. This paper presents a series of architectural improvements to the FPCA that reduce routing delay, increase flexibility and component utilization, and simplify the integration process. Using an fpga containing six FPCAs, we observed average and maximum speedups of 1.60x and 2.40x on a set of arithmetic benchmarks.
fieldprogrammablegatearrays (fpgas) are being used to provide fast Internet Protocol (IP) packet routing and advanced queuing in a highly scalable network switch. A new module, called the field-programmable Port Ex...
详细信息
ISBN:
(纸本)9781581131932
fieldprogrammablegatearrays (fpgas) are being used to provide fast Internet Protocol (IP) packet routing and advanced queuing in a highly scalable network switch. A new module, called the field-programmable Port Extender (FPX), is being built to augment the Washington University Gigabit Switch (WUGS) with reprogrammable logic. FPX modules reside at the edge of the WUGS switching fabric. Physically, the module is inserted between an optical line card and the WUGS gigabit switch back-plane. The hardware used for this project allows ports of the switch populated with an FPX to operate at rates up to 2.4 Gigabits/second. The aggregate throughput of the system scales with the number of switch ports. Logic on the FPX module is implemented with two fpga devices. The first device is used to interface between the switch and the line card, while the second is used to prototype new networking functions and protocols. The logic on the second fpga can be re-programmed dynamically via control cells sent over the network.
暂无评论