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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是791-800 订阅

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Regular fabric design with ambipolar CNTFETs for fpga and structured ASIC applications

Regular fabric design with ambipolar CNTFETs for FPGA and st...

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2010 IEEE/acm international symposium on Nanoscale Architectures, NANOARCH 2010

作者： De Marchi, Michele Ben Jamaa, M. Haykel De Micheli, Giovanni EPFL Lausanne Switzerland CEA-LETI-MINATEC 17 Rue des Martyrs F-38054 Grenoble France

ISBN: (纸本)9781424480180

In this paper, we propose for the first time the application of ambipolar CNTFETs with in-field controllable polarities to design regular fabrics with static logic. We exploit the high expressive power provided by complementary static logic built with ambipolar CNTFETs to design compact and efficient configurable gates. After evaluating a polarity-aware logic design for the configurable gates, we selected a number of gates with an And-Or-Inverter structure and produced a first comparison with existent medium-grained logic blocks, like the Actel ACT1 and 4-input LUTs [1]. Preliminary evaluation of our gates indicates improvements of around 47% over the ACT1 and of about 18x with respect to 4-input LUTs in terms of areaxnormalized delay. ©2010 IEEE.

关键词： field programmable gate arrays (fpga)

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Intel® Nehalem Processor Core Made fpga Synthesizable

Intel® Nehalem Processor Core Made FPGA Synthesizable

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18th acm international symposium on field-programmable gate arrays

作者： Schelle, Graham Collins, Jamison Schuchman, Ethan Wang, Perry Zou, Xiang Chinya, Gautham Plate, Ralf Mattner, Thorsten Olbrich, Franz Hammarlund, Per Singhal, Ronak Brayton, Jim Steibl, Sebastian Wang, Hong Intel Corp Intel Labs Microarchitecture Res Lab Santa Clara CA 95051 USA

ISBN: (纸本)9781605589114

We present a fpga-synthesizable version of the Intel Nehalem processor core, synthesized, partitioned and mapped to a multi-fpga emulation system consisting of Xilinx Virtex-4 and Virtex-5 fpgas. To our knowledge, this is the first time a modern state-of-the-art x86 design with the out-of-order micro-architecture is made fpga synthesizable and capable of high-speed cycle-accurate emulation. Unlike the Intel Atom core which was made fpga synthesizable on a single Xilinx Virtex-5 in a previous endeavor, the Nehalem core is a more complex design with aggressive clock-gating, double phase latch RAMs, and RTL constructs that have no true equivalent in fpga architectures. Despite these challenges, we are successful in making the RTL synthesizable with only 5% RTL code modifications, partitioning the design across five fpgas, and emulating the core at 520 KHz. The synthesizable Nehalem core is able to boot Linux and execute standard x86 workloads with all architectural features enabled.

关键词： Intel Nehalem fpga emulator synthesizable core

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fpga 2008 - Sixteenth acm/sigda international symposium on field-programmable gate arrays

FPGA 2008 - Sixteenth ACM/SIGDA International Symposium on F...

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16th acm/sigda international symposium on field-programmable gate arrays, fpga 2008

ISBN: (纸本)9781595939340

The proceedings contain 24 papers. The topics discussed include: designing with extreme parallelism;high-quality, deterministic parallel placement for fpgas on commodity hardware;enforcing long-path timing closure for fpga routing with path searches on clamped lexicographic spirals;mapping for better than worst-case delays in LUT-based fpga designs;a complexity-effective architecture for accelerating full-system multiprocessor simulations using fpgas;efficient ASIP design for configurable processors with fine-grained resource sharing;pattern-based behavior synthesis for fpga resource reduction;modeling routing demand for early-stage fpga architecture development;and trace-based framework for concurrent development of process and fpga architecture considering process variation and reliability.

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Towards Scalable Placement for fpgas 10

Towards Scalable Placement for FPGAs

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18th acm international symposium on field-programmable gate arrays

作者： Bian, Huimin Ling, Andrew C. Choong, Alexander Zhu, Jianwen Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada

ISBN: (纸本)9781605589114

Placement based on simulated annealing is in dominant use in the fpga community due to its superior quality of result (QoR). However, given the progression of fpga device capacity to the order of 100K LUTs, the long runtime associated with simulated annealing warrants a revisit of other placement paradigms in the context of fpgas. In this paper, we attempt to make a rigorous comparison of a recent crop of academic ASIC placers and VPR, when applied to modern fpga device features and design sizes. We also report a new detailed placer, MDP, based on a new problem formulation of maximum-bipartite matching. We show that MDP is 3X to 7X faster than the detailed placer in Fast-Place, which until now has been the fastest detailed placer publicly available. Furthermore, this speedup occurs while producing comparable or superior QoR. With these results, we speculate promising research directions towards scalable, high quality fpga placement flows that can change the user experience from an overnight wait-time to a coffee break wait-time even on large benchmarks.

关键词： Bipartite Matching Convex Optimization fpga Quadratic Placement

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3D-NonFAR: Three-dimensional non-volatile fpga architecture using phase change memory 10

3D-NonFAR: Three-dimensional non-volatile FPGA architecture ...

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Proceedings of the 16th acm/IEEE international symposium on Low power electronics and design

作者： Chen, Yibo Zhao, Jishen Xie, Yuan Department of Computer Science and Engineering Pennsylvania State University University Park PA 16802 United States

ISBN: (纸本)9781450301466

Memories play a key role in FGPAs in the forms of both programming bits and embedded memory blocks. fpgas using non-volatile memories have been the focus of attention with zero boot-up delay, real-time reconfigurability, and superior energy efficiency. This paper presents a novel threedimensional (3D) non-volatile fpga architecture (3D-Non- FAR) using phase change memory (PCM) and 3D die stacking techniques. Basic structures in a conventional fpga architecture are renovated with PCM, and components are repartitioned and reorganized in 3D-NonFAR to allow an efficient 3D integration of PCM elements. 3D-NonFAR not only preserves the advantages of existing non-volatile fpgas, but also provides high integration density, high performance, and bit-level programmability, which enable PCM as a universal memory replacement in fpgas. Evaluation results show that 3D-NonFAR has smaller footprint, higher performance, and lower power consumption compared with other fpga counterparts. Copyright 2010 acm.

关键词： field programmable gate arrays (fpga)

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FPMR: Map Reduce Framework on fpga A Case Study of RankBoost Acceleration

FPMR: Map Reduce Framework on FPGA A Case Study of RankBoost...

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18th acm international symposium on field-programmable gate arrays

作者： Shan, Yi Wang, Bo Yan, Jing Wang, Yu Xi, Ningyi Yang, Huazhong Tsinghua Univ Dept Elect Engn Tsinghua Natl Lab Informat Sci & Technol Beijing 100084 Peoples R China

ISBN: (纸本)9781605589114

Machine learning and data mining are gaining increasing attentions of the computing society. fpga provides a highly parallel, low power, and flexible hardware platform for this domain, while the difficulty of programming fpga greatly limits its prevalence. MapReduce is a parallel programming framework that could easily utilize inherent parallelism in algorithms. In this paper, we describe FPMR, a MapReduce framework on fpga, which provides programming abstraction, hardware architecture, and basic building blocks to developers. An on-chip processor scheduler is implemented to maximize the utilization of computation resources and achieve better load balancing. An efficient data access scheme is carefully designed to maximize data reuse and throughput. Meanwhile, the FPMR framework hides the task control, synchronization, and communication away from designers so that more attention can be paid to the application itself A case study of RankBoost acceleration based on FPMR demonstrates that FPMR efficiently helps with the development productivity;and the speedup is 31.8x versus CPU-based implementation. This performance is comparable to a fully manually designed version, which achieves 33.5x speedup. Two other applications: SVM, PageRank are also discussed show the generalization of the framework.

关键词： MapReduce fpga framework RankBoost

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A Comprehensive Approach to Modeling, Characterizing and Optimizing for Metastability in fpgas 10

A Comprehensive Approach to Modeling, Characterizing and Opt...

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18th acm international symposium on field-programmable gate arrays

作者： Chen, Doris Singh, Deshanand Chromczak, Jeffrey Lewis, David Fung, Ryan Neto, David Betz, Vaughn Altera Corp Toronto ON Canada

ISBN: (纸本)9781605589114

Metastability is a phenomenon that can cause system failures in digital circuits. It may occur whenever signals are being transmitted across asynchronous or unrelated clock domains. The impact of metastability is increasing as process geometries shrink and supply voltages drop faster than transistor V(t)s. FTGA technologies are significantly affected since leading edge fpgas are amongst the first devices to adopt the most recent process nodes. In this paper, we present a comprehensive suite of techniques for modeling, characterizing and optimizing metastability effects in fpgas. We first discuss a theoretical model of metastability, and verify the predictions using both circuit level simulations and board measurements. Next we show how designers have traditionally dealt with metastability problems and contrast that with the automatic CAD algorithms described in this paper that both analyze and optimize metastability-related issues. Through our detailed experimental results, we show that we can improve the metastability characteristics of a large suite of industrial benchmarks by an average of 268,000 times with our optimization techniques.

关键词： fpga mtbf metastability

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Global Delay Optimization using Structural Choices 10

Global Delay Optimization using Structural Choices

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18th acm international symposium on field-programmable gate arrays

作者： Mishchenko, Alan Brayton, Robert Jang, Stephen Univ Calif Berkeley Dept EECS Berkeley CA 94720 USA

ISBN: (纸本)9781605589114

This paper presents a fast global method for delay optimization after technology mapping. Timing analysis is used to identify timing-critical areas in the mapped network where new structures are synthesized to favor late-arriving signals. Unlike previous methods that make incremental local changes to the mapped network, the proposed method records many alternative structures and defers the final decision to the technology mapper. Experimental results for networks mapped into 6-input look-up tables (6-LUTs) show that the delay is, on average, improved 14% using a realistic delay library for LUTs with variable-pin delays and wire-delay estimation. The area penalty after the delay optimization is about 2% and can be eliminated by area-oriented resynthesis. When the algorithm is compared with DAOmap, the experimental results show 27% logic level reduction while the area is increased by only 1%. The algorithm is also fast and applicable to very large networks. The runtime of the proposed algorithm is 16x and 3x faster than DAOmap for large industrial and academic designs, respectively.

关键词： fpga Technology Mapping Logic Optimization Windowing Boolean Satisfiability Interpolation

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On-Line Sensing for Healthier fpga Systems 10

On-Line Sensing for Healthier FPGA Systems

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18th acm international symposium on field-programmable gate arrays

作者： Zick, Kenneth M. Hayes, John P. Univ Michigan Dept EECS Comp Sci & Engn Div Ann Arbor MI 48109 USA

ISBN: (纸本)9781605589114

Electronic systems increasingly suffer from component variation, thermal hotspots, uneven wearout, and other subtle physical phenomena. Systems based on fpgas have unique opportunities for adapting to such effects. Required, however, is a low-cost, fine-grained method for sensing physical parameters. This paper presents an approach to on-line sensing that includes a compact multi-use sensor implemented in reconfigurable logic, methods for instrumenting an application, and enhanced measurement procedures. The sensor utilizes a highly-efficient counter and improved ring oscillator, and requires just 8 LUTs. We describe how to measure variations in delay, static power, dynamic power, and temperature. We demonstrate the proposed approach with an experimental system based on a Virtex-5. The system is instrumented with over 100 sensors with a total overhead of only 1.3%. Results from thermally-controlled experiments provide some surprising insights and illustrate the power of the approach. On-line sensing can help open the door to physically-adaptive computing, including fine-grained power, reliability, and health management schemes for fpga-based systems.

关键词： fpgas on-line sensing process variation leakage static power dynamic power reliability temperature ring oscillator health management physically-adaptive computing

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High Throughput and Large Capacity Pipelined Dynamic Search Tree on fpga 10

High Throughput and Large Capacity Pipelined Dynamic Search ...

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18th acm international symposium on field-programmable gate arrays

作者： Yang, Yi-Hua E. Prasanna, Viktor K. Univ So Calif Ming Hsieh Dept Elect Engn Los Angeles CA 90089 USA

ISBN: (纸本)9781605589114

We propose a pipelined Dynamic Search Tree (pDST) on fpga which offers high throughput for LOOKUP, INSERT and DELETE operations as well as the capability to perform inplace incremental updates. Based on the pipelined 2-3 tree data structure, our pDST supports one LOOK UP per clock cycle and. maintains tree balance under continual INSERT and DELETE operations. A novel buffered update scheme together with a bi-directional linear pipeline allows the pDST to perform one INSERT or DELETE operation per O (log N) cycles (N being the tree capacity) without stalling the LOOKUP operations. Nodes at each pipeline stage are allocated and freed by a free-node chaining mechanism which greatly simplifies the memory management circuit. Our prototype implementation of a 1.5-level, 32-bit key dual-port pDST requires 192 blocks of 36 Kb BRAMs (64%) and 12.8k LUTs (6.3%) on a Virtex 5 LX330 fpga. The circuit has a maximum capacity of 96k 32-bit keys and clock rate of 135 MHz, supporting 242 million LOOKUPs and concurrently 3.97 million INSERTS or DELETEs per second.

关键词： 2-3 tree B-tree pipelined tree dynamic update incremental update in-place update IP routing OpenFlow

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