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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是801-810 订阅

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fpga Prototyping of an AMBA-Based Windows-Compatible SoC 10

FPGA Prototyping of an AMBA-Based Windows-Compatible SoC

引用

18th acm international symposium on field-programmable gate arrays

作者： Huang, Kan Lu, Junlin Pang, Jiufeng Zheng, Yansong Li, Hao Tong, Dong Cheng, Xu Peking Univ Microprocessor Res & Dev Ctr Beijing 100871 Peoples R China

ISBN: (纸本)9781605589114

For the increasing market of smart phones, mobile internet devices, and ultra-mobile PCs, mainstream vendors propose two approaches: one is based on ARM SoC, and the other is based on power-efficient x86 processor. However, either approach has its own limitation. The ARM-based approach lacks application software while the x86-based approach does not support flexible SoC extension. To overcome the limitations, we propose the PKUnity86 SoC architecture, which is based on AMBA bus architecture to support fast IP integration. Furthermore, it contains a reduced AMD Geode GX2 :processor and several specific designs to support Microsoft Windows and exploit the massive PC software resources. This paper presents two fpga prototypes of PKUnity86: P86-Core and P86-Min. For P86-Core, which is to verify the core of PKUnity86, we change the RTL code of the reduced Geode GX2 to make it fpga-synthesizable and implement it on a Xilinx Virtex-4 LX200 fpga device. We connect the fpga board to a Geode SP4GX22 motherboard so that we can do full-system emulation. For P86-Min, which is to verify the minimum set of PKUnity86, we implement the RTL code on two Xilinx Virtex-4 LX200 fpga devices and emulate the full system on a single fpga board. In addition, we adopt a hardware-software co-development methodology and employ various debug tools to facilitate building P86-Min. Both prototypes reach its own compatibility goal: P86-Core supports Windows XP and previous versions and P86-Min supports Windows 98 and previous versions. The evaluation results show that PKUnity86 achieves Windows compatibility with small hardware overheads and no performance loss.

关键词： x86 AMBA Microsoft Windows fpga

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A Modular NFA Architecture for Regular Expression Matching 10

A Modular NFA Architecture for Regular Expression Matching

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18th acm international symposium on field-programmable gate arrays

作者： Wang, Hao Pu, Shi Knezek, Gabriel Liu, Jyh-Charn Texas A&M Univ Dept Comp Sci & Engn College Stn TX 77840 USA

ISBN: (纸本)9781605589114

We propose a non-deterministic finite automata (NFA) based architecture for regexp scanners on fpga, called CES: the Character Class with Constraint Repetition (CCR) based regExp Scanner. CES is designed to realize a new MIN-MAX counting algorithm, which can solve both the character class ambiguity problem and the overlapped matching problem. CES also supports non-regular Pert grammars such as zero-width pattern and back-reference We propose a CCR-syntax tree and its parsing scheme to map a Perl or POSIX regexp rule to a CES topology. The interconnection patterns, and operational parameters of CCR modules (CCRM), which are the building blocks of CES, can be easily configured by regular memory writes when regexp rules change, without re-synthesis of low-level logic. For implementation, character classes of CCRs are stored in Block RAMs. The MIN-MAX algorithm uses two counters MIN and MAX to resolve the character class ambiguity problem. Two checkpoint counters are employed to implement overlapped matching detection. CES topologies optimized for different types of rules can run in different Partial Reconfigurable Regions (PRR), and can be swapped on the fly by a PRR controller. We developed a tool chain to automate the CES implementation to a Virtex 5 LX110T device. This device can host up to 3000 CCRMs, and run at an estimated throughput of 1.996 Gbps in simulation, and 863 Mbps between a PC and the Virtex 5 board in real tests. The Snort and SpamAssassin rule sets can be parsed and mapped in milliseconds. Once a base CES architecture is synthesized, the physical reconfiguration of a CES on the Virtex 5 LX110T chip can be done in less than a second.

关键词： NFA Regular Expression Character Class Constraint Repetition Overlapped Matching fpga

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A high-performance JPEG2000 decoder based on fpga according to DCI specification

A high-performance JPEG2000 decoder based on FPGA according ...

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international symposium on Photonics and Optoelectronics, SOPO 2010

作者： Xu, Ruixin Xiao, Tie Xu, Chao Peking University Beijing 100871 China

ISBN: (纸本)9781424449644

We present a hardware JPEG2000 decoder architecture based on the DCI specification, which can decode digital cinema frames without accessing any external memory. Besides, an innovative method is proposed to implement decoding process in accordance with the order of output images rather than sequentially to the input code-stream. In this way, not only can the decoded images be outputted immediately, but the storage resources for those middle states and temporary image data can be obviously reduced. ©2010 IEEE.

关键词： field programmable gate arrays (fpga)

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acm/sigda international symposium on field programmable gate arrays - fpga: Foreword

ACM/SIGDA International Symposium on Field Programmable Gate...

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acm/sigda international symposium on field programmable gate arrays - fpga 2008年 iii页

作者： Hutton, Mike Chow, Paul University of Toronto

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fpga-2010 pre-conference workshop on open-source for fpga 10

FPGA-2010 pre-conference workshop on open-source for FPGA

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Proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Shepard Siegel Mike Wirthlin Atomic Rules LLC Auburn NH USA BYU Provo UT USA

ISBN: (纸本)9781605589114

"Open Source", ubiquitous in the software community, has grown to become vital in application domains served by reconfigurable computing. But what exactly is "Open Source", and what are the values and pitfalls it brings? This workshop draws together technologists from academia and industry to share their experiences, opinions, and lessons learned.

关键词： fpga open-source

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Towards 5ps resolution TDC on a dynamically reconfigurable fpga (abstract only) 10

Towards 5ps resolution TDC on a dynamically reconfigurable F...

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Proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Marc-Andre Daigneault Jean Pierre David École Polytechnique de Montréal Montreal PQ Canada

ISBN: (纸本)9781605589114

This paper presents the implementation of a high resolution time-to-digital converter (TDC) on a dynamically reconfigurable fpga. The TDC architecture is based on the Vernier method using two ring oscillators with slightly different frequencies. The proposed oscillators can be calibrated with picoseconds resolution by taking advantage of partial reconfiguration, and moreover recalibrated over time. The results obtained on a Xilinx Virtex-II Pro fpga show that the proposed TDC implementation can achieve unprecedented resolutions (on fpga) as low as 5ps and precisions up to 25ps.

关键词： field programmable gate array time-to-digital converter vernier method dynamic reconfiguration

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A novel architecture for a massively parallel low level vision processing engine on chip

A novel architecture for a massively parallel low level visi...

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IEEE international symposium on Industrial Electronics (ISIE)

作者： Tomasi, Matteo Vanegas, Mauricio Barranco, Francisco Diaz, Javier Ros, Eduardo Univ Granada Comp Architecture & Tecnol Dept E-18071 Granada Spain

ISBN: (纸本)9781424463916

Specific architectures for different low level vision modalities have been developed and described using reconfigurable hardware. Each of them tries to solve a single low level vision problem: optical flow, disparity, segmentation, tracking, etc. We introduce a novel architecture that includes multiple processing engines in a massively parallel low level vision processing engine of very high complexity and performance. Our design is able to process input images and extract at the same time different visual features such as multi-scale stereo, optical flow and local contrast descriptors such as local orientation, energy or phase. The latest hardware design techniques have been employed in order to achieve the presented system with more than 2000 basic processing elements running in parallel. We have based our system in a Harmonic filter image decomposition model based on Gabor-like filters. It has been validated in multiple scenarios in previous works and it allows sharing hardware resources among different vision modalities on the same chip. In this paper we present an fpga based implementation of this intensive processing engine as well as the designing techniques employed. The circuit processes input frames of 512x512 pixels at 28 frames per second.

关键词： fpga based implementation Gabor filters Gabor-like filters Harmonic filter image decomposition model field programmable gate arrays image processing parallel low level vision processing engine reconfigurable architectures reconfigurable hardware

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Programming high performance signal processing systems in high level languages 10

Programming high performance signal processing systems in hi...

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Proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Kees Vissers Devada Varma Vinod Kathail Jeff Bier Don Macmillen Joseph Cavallaro Xilinx San Jose CA USA AutoESL Cupertino CA USA Synfora San Jose CA USA BDTI Berkeley CA USA Stretch Inc. Sunnyvale CA USA Rice University Houston TX USA

No abstract available.

ISBN: (纸本)9781605589114

No abstract available.

关键词： high level programming models signal processing fpga dsp

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Use of Triple Modular Redundancy (TMR) technology in fpgas for the reduction of faults due to radiation in the readout of the ATLAS monitored drift tube (MDT) chambers

Use of Triple Modular Redundancy (TMR) technology in FPGAs f...

引用

2010 IEEE Nuclear Science symposium, Medical Imaging Conference, NSS/MIC 2010 and 17th international Workshop on Room-Temperature Semiconductor X-ray and Gamma-ray Detectors, RTSD 2010

作者： Fras, M. Kroha, H. Loeben, J.V. Reimann, O. Richter, R. Weber, B. Max-Planck-Institut für Physik Föhringer Ring 6 80805 München Germany

ISBN: (纸本)9781424491063

The Triple Modular Redundancy (TMR) technology allows protection of the functionality of fpgas against single event upsets (SEUs). Each logic block is implemented three times with a 2-out-of-3 voter at the output. Thus, the correct logical value is available even if there is an upset bit in one location. We applied TMR to the configuration code of a Virtex-II-2000 fpga, which serves as the on-chamber readout processor of the ATLAS monitored drift tubes (MDTs). We describe the code implementation, results of performance measurements and discuss several limitations of the method. Finally, we present a supplementary technology called scrubbing. It permanently checks the configuration memory while the fpga is operating, and corrects upset configuration bits when necessary. © 2010 IEEE.

关键词： field programmable gate arrays (fpga)

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fpga implementation of highly parallelized decoder logic for network coding (abstract only) 10

FPGA implementation of highly parallelized decoder logic for...

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Proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Sunwoo Kim Won W. Ro Yonsei University Seoul South Korea

ISBN: (纸本)9781605589114

Decoding operation is one of the major performance bottlenecks in network coding applications. To address the problem caused by decoding delay, this paper proposes high-performance decoding logic on the field-programmable gate-array (fpga). A Galois field arithmetic logic unit (GF ALU) is implemented with a full parallelization. We claim that the complexity of hardware is reduced by use of the log and anti-log tables. In addition, the fast arithmetic operation is achieved by the parallelized GF ALU architecture, which allows one-row-calculations of a matrix to be performed concurrently. The decoders for four different sizes of the coefficient matrix have been implemented while the degree of parallelism is preserved for each size. The performance is evaluated by comparing with the performance of the decoding operation both on the ARM processor emulator and a real ARM processor. Using a modern Xilinx Virtex-5 device, the decoding time of 3.5 ms for the size 16 x 16 and 190.5 ms for 128 x 128 has been achieved at the operating frequency of 50MHz, which is equal to 12.7 and 21.7 in terms of speedup.

关键词： network coding fpga fpga implementation galois field arithmetic

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