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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是821-830 订阅

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Heterogeneous-ASIF: an application specific inflexible fpga using heterogeneous logic blocks (abstract only) 10

Heterogeneous-ASIF: an application specific inflexible FPGA ...

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Proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Husain Parvez Zied Marrakchi Habib Mehrez Université Pierre et Marie Curie Paris France

ISBN: (纸本)9781605589114

An Application Specific Inflexible fpga (ASIF) is an fpga with reduced flexibility that can implement a set of application circuits which will operate at different times. Application circuits are initially placed and routed on an fpga in such a way that the total routing switches used in the fpga architecture are minimized. Later all unused routing resources are removed from the fpga to generate an ASIF. An ASIF which is reduced from a heterogeneous fpga (i.e. containing hard-blocks such as Multipliers, Adders and RAMS etc) is called as a Heterogeneous-ASIF. This work shows that a standard-cell based Heterogeneous-ASIF using Multipliers, Adders and Look-Up-Tables for a set of 10 opencores application circuits is 85% smaller in area than a single driver fpga using the same type of blocks, and only 24% larger than the sum of areas of their standard-cell based ASIC version. If the Look-Up-Tables are replaced with a set of repeatedly used hard logic gates (such as AND gate, OR gate, FLIP-FLOPS etc), the ASIF becomes 89% smaller than the fpga and 3% smaller than the sum of ASICs. The area gap between ASIF and sum of ASICs can be further reduced if repeatedly used groups of standard-cell logic gates in an ASIF are designed in full-custom. One of the major advantages of an ASIF is that just like an fpga, an ASIF can also be reprogrammed to execute new or modified circuits, but at a very limited scale. A new CAD flow is presented to map application circuits on an ASIF.

关键词： architecture application specific cad asif fpga

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Automatic tool flow for shift-register-LUT reconfiguration: making run-time reconfiguration fast and easy (abstract only) 10

Automatic tool flow for shift-register-LUT reconfiguration: ...

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Proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Brahim Al Farisi Karel Bruneel Harald Devos Dirk Stroobandt Ghent University Ghent Belgium

ISBN: (纸本)9781605589114

The Shift-Register-Lut (SRL) functionality is a powerful extension of Xilinx fpga architectures and has been used successfully in many applications. If routing is kept fixed, these SRLs can also be used for run-time reconfiguration. So far, this technique has mainly been used to reconfigure specialized functions. In contrast, we propose a generic tool flow that uses SRLs for fast run-time reconfiguration of general data folding applications. We show that, in such an automatic toolflow, SRL reconfiguration is over two orders of magnitude faster than run-time reconfiguration using the ICAP. It thus makes run-time reconfiguration viable for applications with a more dynamic behaviour. Our generic tool flow is also very easy to use since the designer only has to annotate slowly varying signals in an RTL HDL description, while the tool flow takes care of all the rest.

关键词： fpga icap reconfigurable computing run-time reconfiguration tmap parameterizable configurations srl

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Application of a reconfigurable computing cluster to ultra high throughput genome resequencing (abstract only) 10

Application of a reconfigurable computing cluster to ultra h...

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Proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Kristian Stevens Henry Chen Terry Filiba Peter McMahon Yun S. Song University of California Davis Davis CA USA Berkeley Wireless Research Center Berkeley CA USA Stanford University Stanford CA USA University of California Berkeley Berkeley CA USA

ISBN: (纸本)9781605589114

Recent advances in ultra-high-throughput sequencing technology are allowing researchers to generate immense amounts of raw data in the form of short reads from ultra high-throughput platforms. We demonstrate how field programmable gate arrays (fpgas) may be used to address computing challenges associated with next-generation genome sequencing. A common prerequisite to utilizing data generated by next-generation sequencers is alignment to a reference genome. While dynamic programming (DP) alignment algorithms are generally avoided on conventional architectures due to their computational complexity, they can be tailored for efficient implementation on systolic architectures. We implemented application-specific DP algorithms for aligning data from ultra high throughput sequencers utilizing a reconfigurable computing cluster of BEE2 boards. In our design each fpga is capable of rapidly aligning multiple sequences in parallel against a long reference genome using multiple systolic arrays. The reconfigurable cluster proves to be scalable and capable of processing real world datasets as large as the Human genome in time proportional to data acquisition. We examine the advantages and practicality of this approach by benchmarking using Illumina sequence data from a large high-throughput sequencing project. We addressed an open question of whether a DP algorithm efficiently implementable on an fpga can offer a quantitative improvement over the heuristic methods currently employed. Our extensive validation showed that application specific algorithms and computing hardware can provide more accurate results than current heuristic methods and may be particularly useful in circumstances where error rates or evolutionary divergence is high. While directly addressing the important problem of assembling genomes, the methods presented are also relevant to many other "omics" research applications.

关键词： genome resequencing reconfigurable logic fpga acceleration

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Minimizing partial reconfiguration overhead with fully streaming DMA engines and intelligent ICAP controller (abstract only) 10

Minimizing partial reconfiguration overhead with fully strea...

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Proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Shaoshan Liu Richard Neil Pittman Alessandro Forin University of California Irvine Irvine CA USA Microsoft Research Redmond WA USA

ISBN: (纸本)9781605589114

Configuration overhead seriously limits the usefulness of fpga partial reconfiguration. In this paper, we propose a combination of two techniques to minimize the partial reconfiguration performance overhead. First, we design and implement fully streaming DMA engines to nearly saturate configuration throughput. Second, we exploit a simple form of configuration data redundancy to compress the configuration bitstreams, and we implement an intelligent ICAP controller to perform decompression at runtime. The results show that our design achieves an effective configuration data transfer throughput of up to 1.2 Gbytes/s, which actually well surpasses the theoretical upper bound of the data transfer throughput, 400 Mbytes/s. Specifically, our fully streaming DMA engines reduce the configuration time from the range of seconds to the range of milliseconds, a more than 1000-fold improvement. In addition, our simple compression scheme achieves up to 75% reduction of bitstream size and results in a decompression circuit with negligible hardware overhead.

关键词： fpga partial reconfiguration

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Multiplier architectures for fpga double precision functions (abstract only) 10

Multiplier architectures for FPGA double precision functions...

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Proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Y. Hamid Martin Langhammer Altera Corporation Penang Malaysia Altera Corporation High Wycombe United Kingdom

ISBN: (纸本)9781605589114

fpga devices are now more capable at supporting floating point applications, but double precision IEEE754 systems are still very challenging to implement, with large amounts of logic, routing, and DSP resources needed. Double precision multiplier operators, requiring 54x54 multiplier cores, are now directly supported in the fabric, however, multiplier based algorithms for algebraic and elementary functions typically require larger multiplier functions, typically in excess of 60x60 bits precision. This paper will use the example of a double precision exp (ex) to explore tradeoffs with multiplier architectures mapped to current fpgas devices. Different types of the larger multiplier architectures, including direct implementations and Karatsuba-Ofman algorithms will be compared, including their effect on the resource requirements and system performance of the exp function. Smaller multiplier architectures, which introduce a small maximum functional error, will also be *** large multiplier architectures can provide the same accuracy with increased system performance, with up to 33% less multiplier resources. Smaller multiplier will reduce the multiplier resources by up to 50%, albeit with a small maximum error, in the range of 5 ulp.

关键词： fpga floating point

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An architecture for graphics processing in an fpga (abstract only) 10

An architecture for graphics processing in an FPGA (abstract...

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Proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Marcus Dutton David Keezer Georgia Institute of Technology Atlanta GA USA

ISBN: (纸本)9781605589114

Graphics processing is most often accomplished in standalone ASICs that were originally designed for gaming applications. The graphics processors produce visually appealing functionality based upon 3D rendering algorithms, but they can also require large amounts of power and typically have only short-term device availability. This paper proposes a novel architecture for graphics processing in an fpga that is motivated by industrial applications that require low power, high reliability, low cost, and long-term device availability. Due to resource constraints and architectural constructs, many traditional graphics processing concepts do not translate well to fpgas; hence, a graphics processing architecture crafted specifically for fpgas is needed. The proposed architecture provides a high degree of scalability and flexibility to allow customization for unique applications, and it also features the migration of technology that previously has been used only for packet processing. The unique multi-threaded packet processing engine accelerates the line rasterization with a careful partitioning of the processing across software and hardware. The baseline architecture, which can be scaled for higher performance through parallelisms, will be capable of rasterizing over 50 million pixels per second -- more than enough for any application with XGA resolution. Future work will focus on the complete implementation and optimization of the architecture as well as an extension to support general-purpose computations (GPGPU) on the fpga-based graphics processor.

关键词： fpga flexibility architecture scalability gpu

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Memory efficient string matching: a modular approach on fpgas (abstract only) 10

Memory efficient string matching: a modular approach on FPGA...

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Proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Hoang Le Yi-Hua Yang Viktor K. Prasanna University of Southern California Los Angeles CA USA

ISBN: (纸本)9781605589114

Network Intrusion Detection Systems (NIDSs) have emerged as powerful tools for detecting and preventing malicious attacks over both the Internet and Intranet. String matching, which is one of the most important functions of NIDS, demands exceptionally high performance to match the content of network traffic against a predefined database of malicious patterns. Much work has been done in this field; however, they result in low memory efficiency\footnote{The memory efficiency (in bytes/char) is defined as the ratio of the amount of the required storage memory (in bytes), and the size of the dictionary (number of characters).}. Due to the available on-chip memory and the number of I/O pins of field programmable gate arrays (fpgas), state-of-the-art designs cannot support large dictionaries without using high-latency external DRAM. We propose a novel Memory efficient Architecture for large-scale String Matching, namely MASM, based on pipelined binary search tree. Our design provides a high-throughput matching module, which can be used as the building block to process arbitrary-length patterns. With memory efficiency close to 1 byte/char, MASM can support a dictionary\footnote The size of a dictionary is the total number of characters in all the patterns in the dictionary. of over 4 MB (regardless of the size of the alphabet), using a single state-of-the-art fpga device. This efficiency is comparable to that of a Ternary Content Addressable Memory (TCAM)-based solution. The architecture can also be easily partitioned, so as to use external SRAM to handle even larger dictionaries of over 8 MB. Our implementation results show a sustained throughput of 3.2 Gbps, even when external SRAM is used. The MASM module can be simply duplicated to accept multiple characters per cycle, leading to scalable throughput with respect to the number of characters processed in each cycle. Dictionary update involves only rewriting the memory content, which can be done quickly without reconfigur

关键词： packet filtering fpga deep packet classification

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A dependency graph based methodology for parallelizing HLL applications on fpga (abstract only) 10

A dependency graph based methodology for parallelizing HLL a...

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Proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Sunita Chandrasekaran Shilpa Shanbagh Douglas L. Maskell Nanyang Technological University Singapore Singapore

ISBN: (纸本)9781605589114

Reconfigurable computing is an exciting new area of research. It opens up a number of new computing paradigms with the potential to significantly change the embedded computing landscape. Unfortunately, as with any new concept, there is much to be done before it can be brought into the mainstream. Reconfigurable computing needs to be made more usable by the general computing community by making the application mapping process more user transparent. We need to be able to efficiently exploit the parallelism and high communications bandwidth available in reconfigurable computing systems, such as provided by fpga devices. In this paper we propose a framework to map C-based applications to an fpga based system. The framework relies on dependency based analysis information obtained from a high level Intermediate Representation (IR) of the C-Application. The dependencies have a major impact on the instruction flow and the parallelism of the algorithms when implemented on fpga based high performance computing platforms. We demonstrate the importance of these dependencies in algorithms by examining a compute intensive bio-informatics application. Targeting on a Xilinx Virtex 5 XC5VFX70T fpga, our place and route results achieved 92% of the clock frequency achieved by using a manual design of the same application. The contribution in this paper is to provide a semi-automated approach to generate hardware for fpga based systems through a high level data dependency graphical IR.

关键词： data dependency analysis bioinformatics smith-waterman algorithm sequence alignment fpgas

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LUT-based fpga technology mapping for reliability (abstract only) 10

LUT-based FPGA technology mapping for reliability (abstract ...

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Proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Jason Cong Kirill Minkovich UCLA Los Angeles CA USA

ISBN: (纸本)9781605589114

As device size shrinks to the nanometer range, fpgas are increasingly prone to manufacturing defects. We anticipate that the ability to tolerate multiple defects will be very important at 32nm and beyond. It is common for defect points to occur in the lookup table (LUT) configuration bits, which are crucial to the correct operation of fpgas. In this work we will present an error analysis technique that is able to efficiently calculate the number of critical bits needed to implement each LUT. We will perform this analysis using an overlapping window-based method which allows for accurate and efficient error calculations. This new windowing technique can approximate the complete don't cares (CDC) within 2.5%. This is 5X faster than a 100k Monte Carlo simulation and 26% more accurate. Compared to the windowing method used in the ABC synthesis system, our new method is 2.77X more accurate for computing the CDC. We then use our new windowing in an fpga mapping algorithm to reduce the number of possible faults. This will allow the design to have a much higher success of functioning correctly when implemented on a faulty fpga. By using our algorithm, we are able to reduce the number of possible faults by over 12% with no area increase. Our work shows that it is possible to effectively increase the reliability of a design in the presence of LUT faults in fpgas.

关键词： fpga lookup table windowing logic synthesis don't cares technology mapping error analysis

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fpga based chip emulation system for test development and verification of analog and mixed signal circuits (abstract only) 10

FPGA based chip emulation system for test development and ve...

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Proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Rahul Bhattachrya Santosh Biswas Siddhartha Mukhopadhyay IIT Kharagpur Kharagpur India IIT Guwahati Guwahati India

ISBN: (纸本)9781605589114

Prototyping on fpga has become a main stream verification methodology for hardware design, test development, software co-design etc. in the area of digital VLSI. In the case of test development, fpga serves as a virtual DUT (Design under Test) and test patters are applied from automatic test equipment (ATE). This verifies not only the chip with design for test (DFT) circuitry and test program but also the entire test setup involving virtual DUT, load board, interconnections with ATE etc. Although, fpga based platform is used widely for test program verification of digital ICs, this technique is not used for analog/mixed signal (AMS) circuits because of the difficulty in implementing AMS circuits in FPFAs. This work is concerned with the development of a test emulation platform, termed as hand-in-hand test flow, of AMS circuits based on fpga. The proposed methodology exploits fixed-point modeling and DSP implementation technique facilitated by latest fpgas to model the AMS circuits. The proposed hand-in-hand test flow for AMS circuits will help the test engineers to start their test plan concurrently with the design engineers and validate them much prior to the first silicon. We have illustrated the proposed scheme using the case study of an analog phase locked loop (PLL) on Xilinx® Virtex"-4 fpga. The fpga emulation results show that performance of the emulated analog PLL (e.g., acquisition characteristics, step response) matches well with that of behavioral simulation.

关键词： concurrent test development ams testing behavioral modeling

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