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检索条件"任意字段=FPGA 2000: ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 1376 条记录，以下是861-870 订阅

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High-performance, energy-efficient platforms in-socket fpga accelerators

High-performance, energy-efficient platforms in-socket FPGA ...

引用

7th acm sigda international symposium on field-programmable gate arrays, fpga'09

作者： Ling, Liu Oliver, Neal Bhushan, Chitlur Qigang, Wang Chen, Alvin Wenbo, Shen Zhihong, Yu Sheiman, Arthur McCallum, Ian Grecco, Joseph Mitchel, Henry Dong, Liu Gupta, Prabhat Intel Corporation

ISBN: (纸本)9781605584102

Growing demand for energy-efficient, high-performance systems has resulted in the growth of innovative heterogeneous computing system architectures that use fpgas. fpga-based architectures enable designers to implement custom instruction streams executing on potentially thousands of compute elements. Traditionally, fpgas have been used as compute elements on PCI devices;however, this does not allow the fpgas to be coprocessors. This paper describes a high-performance system architecture that is based on the Intel Xeon platform in which one or more fpgas, acting as application accelerators, replace one or more processors in a dual/multi-processor (DP/MP) platform. The fpga is thus connected directly to the Front Side Bus (FSB) and enjoys the same privileges as a processor, i.e., full participation in the coherency protocol, unrestricted access to system memory and to other processors via the high bandwidth, and low latency connection to the FSB. In addition, we also describe a software layer called the "Accelerator Abstraction Layer (AAL)", which provides a uniform, hardware- and/or platform-independent application interface. Applications written on AAL can be ported to multiple platforms that have different types of accelerators and the application does not have to be modified. In addition, the AAL also enables the developer/user to reprogram the fpga on the fly (analogous to an operating system context switch) thereby utilizing the programmable nature of the fpga. The resulting hardware/software stack creates a flexible and powerful platform for accelerator innovation and deployment. Copyright 2009 acm.

关键词： field programmable gate arrays (fpga)

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Large-scale wire-speed packet classification on fpgas

Large-scale wire-speed packet classification on FPGAs

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7th acm sigda international symposium on field-programmable gate arrays, fpga'09

作者： Jiang, Weirong Prasanna, Viktor K. Ming Hsieh Department of Electrical Engineering University of Southern California Los Angeles CA 90089 United States

ISBN: (纸本)9781605584102

Multi-field packet classification is a key enabling function of a variety of network applications, such as firewall processing, Quality of Service differentiation, traffic billing, and other value added services. Although a plethora of research has been done in this area, wire-speed packet classification while supporting large rule sets remains difficult. This paper exploits the features provided by current fpgas and proposes a decision-tree-based, two-dimensional dual-pipeline architecture for multi-field packet classification. To fit the current largest rule set in the on-chip memory of the fpga device, we propose several optimization techniques for the stateof- the-art decision-tree-based algorithm, so that the memory requirement is almost linear with the number of rules. Specialized logic is developed to support varying number of branches at each decision tree node. A tree-to-pipeline mapping scheme is carefully designed to maximize the memory utilization. Since our architecture is linear and memory based, on-the-fly update without disturbing the ongoing operations is feasible. The implementation results show that our architecture can store 10K real-life rules in on-chip memory of a single Xilinx Virtex-5 fpga, and sustain 80 Gbps (i.e. 2 OC-768 rate) throughput for minimum size (40 bytes) packets. To the best of our knowledge, this work is the first fpga-based packet classification engine that achieves wire-speed throughput while supporting 10K unique rules. Copyright 2009 acm.

关键词： field programmable gate arrays (fpga)

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Scalable don't-care-based logic optimization and resynthesis

Scalable don't-care-based logic optimization and resynthesis

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7th acm sigda international symposium on field-programmable gate arrays, fpga'09

作者： Mishchenko, Alan Brayton, Robert Jiang, Jie-Hong Roland Jang, Stephen Department of EECS University of California Berkeley United States Department of EE National Taiwan University Taiwan Xilinx Inc. San Jose CA United States

ISBN: (纸本)9781605584102

We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability and the scope of optimization. The proposed resynthesis (a) is capable of substantial logic restructuring, (b) is customizable to solve a variety of optimization tasks, and (c) has reasonable runtime on industrial designs. The approach uses don't cares computed for a window surrounding a node and can take into account external don't cares (e.g. unreachable states). It uses a SAT solver and interpolation to find a new representation for a node. This representation can be in terms of inputs from other nodes in the window thus effecting Boolean re-substitution. Experimental results on 6-input LUT networks after high effort synthesis show substantial reductions in area and delay. When applied to 20 large academic benchmarks, the LUT count and logic level is reduced by 45.0% and 12.2%, respectively. The longest runtime for synthesis and mapping is about two minutes. When applied to a set of 14 industrial benchmarks ranging up to 83K 6-LUTs, the LUT count and logic level is reduced by 11.8% and 16.5%, respectively. Experimental results on 6-input LUT networks after high-effort synthesis show substantial reductions in area and delay. The longest runtime is about 30 minutes. Copyright 2009 acm.

关键词： field programmable gate arrays (fpga)

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Automatic bus macro placement for partially fpga designs

Automatic bus macro placement for partially FPGA designs

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7th acm sigda international symposium on field-programmable gate arrays, fpga'09

作者： Carver, Jeffrey M. Pittman, Richard N. Forin, Alessandro Utah State University 1400 Old Main Hill Logan UT 84322 United States Microsoft Research One Microsoft Way Redmond WA 98052 United States

ISBN: (纸本)9781605584102

Dynamic Partial Reconfiguration of fpgas partitions the configurable logic fabric into static and reconfigurable regions. The reconfigurable regions' functionality changes at run time while the static regions continue unperturbed. The reconfigurable and static regions interface via fixed connection points ("bus macros"). We introduce the notion of a fitness score as the measure of how well the combined designs meet their timing constraints, subject to a given bus macro placement. We present a tool that uses design-space exploration to obtain automatic, near-optimal placements. The tool achieves 76% better fitness scores over manual placements. The location of the bus macros around a region has a noticeable impact on the timings, and we found that this is accurately reflected on our fitness score. We also found that following the accepted best design practices leads to quantifiably sub-optimal placements, underscoring the need for such a tool. Copyright 2009 acm.

关键词： Buses

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A multi-fpga 10x-real-time high-speed search engine for a 5000-word vocabulary speech recognizer

A multi-FPGA 10x-real-time high-speed search engine for a 50...

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7th acm sigda international symposium on field-programmable gate arrays, fpga'09

作者： Lin, Edward C. Rutenbar, Rob A. Electrical and Computer Engineering Carnegie Mellon University R. Forbes Ave Pittsburgh PA 15213 United States

ISBN: (纸本)9781605584102

Today's best quality speech recognition systems are implemented server software. These systems fully occupy the resources of a highend to deliver results at real-time speed: each hour of audio requires a significant fraction of an hour of computation for . This is profoundly limiting for applications that extreme recognition speed, for example, high-volume tasks such as video indexing (e.g., YouTube), or high-speed tasks such as triage of homeland security intelligence. We describe the acrhitecture and implementation of one critical component - the backend search stage - of a high-speed, large-vocabulary . Implemented on a multi-fpga Berkeley Emulation 2 (BEE2) platform, we handle a standard 5000-word Wall Journal speech benchmark. Our backend search engine can on average 10 times faster than real-time running at 100 , i.e, 10x faster than real-time, with negligible degradation in , running at a clock rate 30x slower than a conventional . To the best of our knowledge, this is both the most , and the fastest recognizer ever to be realized in a hardware form. Copyright 2009 acm.

关键词： Search engines

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VPR 5.0: fpga CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling

VPR 5.0: FPGA CAD and architecture exploration tools with si...

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7th acm sigda international symposium on field-programmable gate arrays, fpga'09

作者： Luu, Jason Kuon, Ian Jamieson, Peter Campbell, Ted Ye, Andy Fang, Wei Mark Rose, Jonathan Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto Toronto ON Canada

ISBN: (纸本)9781605584102

The VPR toolset [6, 7] has been widely used to perform fpga architecture and CAD research, but has not evolved over the past decade to include many architectural features now present in modern fpgas. This paper describes a new version of the toolset that includes four significant features: first, it now supports a broad range of single-driver routing architectures [29, 4, 16]. Single-driver routing has significantly different architectural and electrical properties from the multi-driver approach previously modelled, and is now employed in the majority of fpgas sold. Second, the new release can now model a heterogeneous selection of hard logic blocks, which could include the hard memory and multipliers that are now ubiquitous in fpgas. Third, we provide optimized electrical models of a wide range of architectures in different process technologies, including a range of area-delay tradeoffs for each single architecture. Prior releases of VPR did not publish even one architecture file with accurate resistance and capacitance parameters. Finally, to maintain robustness and to support future development the release includes a set of regression tests to check functionality and quality of result of the output of the tools. To illustrate the use of the new features, we present a new look at the fpga area vs. logic block LUT size question that shows that small LUT sizes, with the use of carefully optimized electrical design and single-driver architectures, have better area (relative to 4-LUTs) than previously thought. Another experiment shows that several of the previous architectural results are invariant in moving from multi-driver to single-driver routing architecture and across a range of process technologies. Copyright 2009 acm.

关键词： field programmable gate arrays (fpga)

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Intel atom processor core made fpga-synthesizable

Intel atom processor core made FPGA-synthesizable

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7th acm sigda international symposium on field-programmable gate arrays, fpga'09

作者： Wang, Perry H. Collins, Jamison D. Weaver, Chris T. Kuttanna, Belliappa Salamian, Shahram Chinya, Gautham N. Schuchman, Ethan Schilling, Oliver Doil, Thorsten Steibl, Sebastian Wang, Hong Microarchitecture Research Lab Corporate Technology Group Intel Corporation Atom Processor Architecture Mobility Group Intel Corporation Germany Microprocessor Lab Corporate Technology Group Intel Corporation Germany

ISBN: (纸本)9781605584102

We present an fpga-synthesizable version of the Intel Atom processor core, synthesized to a Virtex-5 based fpga emulation system. To make the production Atom design in SystemVerilog synthesizable through industry standard EDA tool flow, we transformed and mapped latches in the design, converted clock gating, and replaced nonsynthesizable constructs with fpga-synthesizable counterparts. Additionally, as the target fpga emulator is hosted on a PC platform with the Pentium-based CPU socket that supports a significantly different front side bus (FSB) protocol from that of the Atom processor, we replaced the existing bus control logic in the Atom core with an alternate FSB protocol to communicate with the rest of the PC platform. With these efforts, we succeeded in synthesizing the entire Atom processor core to fit within a single Virtex-5 LX330 fpga. The synthesizable Atom core runs at 50Mhz on the Pentium PC motherboard with fully functional I/O peripherals. It is capable of booting off-the-shelf MS-DOS, Windows XP and Linux operating systems, and executing standard x86 workloads. Copyright 2009 acm.

关键词： field programmable gate arrays (fpga)

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A Multiprocessor Self-reconfigurable JPEG2000 Encoder

A Multiprocessor Self-reconfigurable JPEG2000 Encoder

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23rd IEEE international Parallel and Distributed Processing symposium

作者： Tumeo, Antonino Borgio, Simone Bosisio, Davide Monchiero, Matteo Palermo, Gianluca Ferrandi, Fabrizio Sciuto, Donatella Politecn Milan DEI Via Ponzio 34-5 I-20133 Milan Italy HP Lab Palo Alto CA 94304 USA

ISBN: (纸本)9781424437511

This paper presents a multiprocessor architecture prototype on a field programmable gate arrays (fpga) with support for hardware and software multithreading. Thanks to partial dynamic reconfiguration, this system can, at run time, spawn both software and hardware threads, sharing not only the general purpose soft-cores present in the architecture but also area on the fpga. While on a standard single processor architecture the partial dynamic reconfiguration requires the processor to stop working to instantiate the hardware threads, the proposed solution hides most of the reconfiguration latency through the parallel execution of software threads. We validate our framework on a JPEG 2000 encoder, showing how threads are spawned, executed and joined independently of their hardware or software nature. We also show results confirming that, by using the proposed approach, we are able to hide the reconfiguration time.

关键词： Dynamic models

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Emerging application domains: research challenges and opportunities for fpgas 09

Emerging application domains: research challenges and opport...

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Proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Jason H. Anderson University of Toronto Toronto ON Canada

ISBN: (纸本)9781605584102

Communications infrastructure, data processing and industrial electronics are the cornerstone application areas for programmable logic today. But what are the application domains of tomorrow? What nascent application areas could explode the growth of programmable logic usage and expand the programmable market? In this workshop, we will hear speakers from industry and academia talk about the emerging application areas for fpgas and the challenges and opportunities in these areas. We will consider how programmable hardware and the associated tools should be enhanced to become better-suited to tomorrow's applications. The overarching aim of the workshop is to seed ideas in the research community by giving an applications perspective of the fertile topics for future research on fpga architecture, CAD and applications.

关键词： high-performance computing field-programmable gate array applications performance power fpga reconfigurable computing

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A multiprocessor self-reconfigurable JPEG2000 encoder

A multiprocessor self-reconfigurable JPEG2000 encoder

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international symposium on Parallel and Distributed Processing (IPDPS)

作者： Antonino Tumeo Simone Borgio Davide Bosisio Matteo Monchiero Gianluca Palermo Fabrizio Ferrandi Donatella Sciuto Politecnico di Milano-DEI Milan Italy HP Laboratories Palo Alto CA USA

关键词： Hardware field programmable gate arrays Yarn Computer architecture Delay Application specific integrated circuits Reconfigurable logic Software prototyping Embedded system Logic devices

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