We present an architecture for a synthesizable datapath-oriented fieldprogrammablegate Array (fpga) core which can be used to provide post-fabrication flexibility to a System-on-Chip (SoC). Our architecture is optim...
详细信息
ISBN:
(纸本)9781595936004
We present an architecture for a synthesizable datapath-oriented fieldprogrammablegate Array (fpga) core which can be used to provide post-fabrication flexibility to a System-on-Chip (SoC). Our architecture is optimized for bus-based operations that are common in signal processing and computation intensive applications. It employs a directional routing architecture, which allows it to be synthesized using standard ASIC design tools and flows. We also describe a proof-of-concept layout of our core. It is shown that the proposed architecture is significantly more area efficient than the best previously reported synthesizable programmable logic core.
Recent research has developed a new, entirely digital architecture, called X-ORCA, that determines the phase shift of two periodic signals with a resolution as good as about 20 Ps. This paper incorporates the X-ORCA s...
详细信息
ISBN:
(纸本)9781450311557
Recent research has developed a new, entirely digital architecture, called X-ORCA, that determines the phase shift of two periodic signals with a resolution as good as about 20 Ps. This paper incorporates the X-ORCA system into a wireless experimental setup to form a localization system. The practical experiments utilize a 2.484 GHz transmitter and run the X-ORCA core on a Cyclone II fpga. The results indicate that this simple localization system easily yields a spatial resolution in the sub-millimeter range.
RAKE receivers are widely used in the wireless communications industry. Currently, custom VLSI is the most popular implementation. programmable and reconfigurable logic implementations are becoming more attractive bec...
详细信息
ISBN:
(纸本)9781581131932
RAKE receivers are widely used in the wireless communications industry. Currently, custom VLSI is the most popular implementation. programmable and reconfigurable logic implementations are becoming more attractive because of their flexibility and due to technology advancements. We have implemented a RAKE receiver on an Annapolis Wildforce board with four Xilinx 4000 family chips for a total of 100,000 gate equivalents. Our system is able to implement a RAKE receiver for underwater data communication systems that works in real time. We also investigate mapping a RAKE receiver to a Virtex chip for real-time atmospheric wireless communication.
Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the effects of variations. The fpga communi...
详细信息
ISBN:
(纸本)9781595936004
Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the effects of variations. The fpga community on the other hand, has only recently started focussing on the effects of variations. This paper presents a comparative study of the impact of variations on designs mapped to fpgas and ASICs to get a measure of the severity of the problem in both the fpga and ASIC domains. We also propose a variation aware router that reduces the yield loss by 7.61X, or the circuit delay by 3.95% for the same yield for the MCNC benchmarks.
The continuously widening gap between the Non-Recurring Engineering (NRE) and Recurring Engineering (RE) costs of producing Integrated Circuit (IC) products in the past few decades gives high incentives to unauthorize...
详细信息
ISBN:
(纸本)9781450311557
The continuously widening gap between the Non-Recurring Engineering (NRE) and Recurring Engineering (RE) costs of producing Integrated Circuit (IC) products in the past few decades gives high incentives to unauthorized cloning and reverse-engineering of ICs. Existing IC Digital Rights Management (DRM) schemes often demands high overhead in area, power, and performance, or require non-volatile storage. Our goal is to develop a novel Intellectual Property (IP) protection technique that offers universal protection to both Application-Specific integrated Circuits (ASIC) and field-programmablegate-arrays (fpgas) from unauthorized manufacturing and reverse engineering. In this paper we show a proof-of-concept implementation of the basic elements of the technique, as well as a case study of applying the anti-cloning technique to a nontrivial fpga design.
Variations in the semiconductor fabrication process results in variability, in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The reconfigurability of field-programmable...
详细信息
ISBN:
(纸本)9781595936004
Variations in the semiconductor fabrication process results in variability, in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The reconfigurability of field-programmablegatearrays presents the opportunity to compensate for within-die delay variability. This paper presents three reconfiguration-based strategies for compensating within-die stochastic delay variability in fpgas: reconfiguring the entire fpga, relocating subcircuits within an fpga, and reconfiguring signal paths within a design. The yield of each strategy is analysed and compared with worst-case design and statistical static timing analysis (SSTA). It is demonstrated that significant improvements in circuit yield and timing are possible using SSTA alone, and these improvements call be enhanced by employing reconfiguration-based techniques.
Many hardware systems for stereo vision have been proposed. Their processing speed is very fast, but the algorithms used in them are limited in order to achieve the high processing speed by simplifying the sequences o...
详细信息
ISBN:
(纸本)9781450311557
Many hardware systems for stereo vision have been proposed. Their processing speed is very fast, but the algorithms used in them are limited in order to achieve the high processing speed by simplifying the sequences of the memory accesses and operations. The error rates by them can not compete with those by software programs. In this paper, we describe an fpga implementation of a tree-structured dynamic programming algorithm. The computational complexity of this algorithm is higher than those by previous hardware systems, but the processing speed of our system is still fast enough for real-time applications, and its error rate is competitive with software algorithms.
With the expiration of the Data Encryption Standard (DES) in 1998, the Advanced Encryption Standard (AES) development process is well underway. It is hoped that the result of the AES process will be the specification ...
详细信息
With the expiration of the Data Encryption Standard (DES) in 1998, the Advanced Encryption Standard (AES) development process is well underway. It is hoped that the result of the AES process will be the specification of a new non-classified encryption algorithm that will have the global acceptance achieved by DES as well as the capability of long-term protection of sensitive information. The technical analysis used in determining which of the potential AES candidates will be selected as the Advanced Encryption Algorithm includes efficiency testing of both hardware and software implementations of candidate algorithms. Reprogrammable devices such as fieldprogrammablegatearrays (fpgas) are highly attractive options for hardware implementations of encryption algorithms as they provide cryptographic algorithm agility, physical security, and potentially much higher performance than software solutions. This contribution investigates the significance of an fpga implementation of Serpent, one of the Advanced Encryption Standard candidate algorithms. Multiple architecture options of the Serpent algorithm will be explored with a strong focus being placed on a high speed implementation within an fpga in order to support security for current and future high bandwidth applications. One of the main findings is that Serpent can be implemented with encryption rates beyond 4 Gbit/s on current fpgas.
Good fpga placement is crucial to obtain the best Quality of Results (QoR) from fpga hardware. Although many published global placement techniques place objects in a continuous ASIC-like environment, fpgas are discret...
详细信息
ISBN:
(纸本)9781450311557
Good fpga placement is crucial to obtain the best Quality of Results (QoR) from fpga hardware. Although many published global placement techniques place objects in a continuous ASIC-like environment, fpgas are discrete in nature, and a continuous algorithm cannot always achieve superior QoR by itself. Therefore, discrete fpga-specific detail placement algorithms are used to improve the global placement results. Unfortunately, most of these detail placement algorithms do not have a global view. This paper presents a discrete "middle" placer that fills the gap between the two placement steps. It works like simulated annealing, but leverages various acceleration techniques. It does not pay the runtime penalty typical of simulated annealing solutions. Experiments show that with this placer, final QoR is significantly better than with the global-detail placer approach.
暂无评论