the proceedings contain 131 papers. the topics discussed include: customizable domain-specific computing;in search of agile hardware;the evolution of architecture exploration of programmable devices;MUCCRA-cube: a 3D ...
ISBN:
(纸本)9781424438921
the proceedings contain 131 papers. the topics discussed include: customizable domain-specific computing;in search of agile hardware;the evolution of architecture exploration of programmable devices;MUCCRA-cube: a 3D dynamically reconfigurable processor with inductive-coupling link;fast critical sections via thread scheduling for FPGA-based multithreaded processors;a biophysically accurate floating point somatic neuroprocessor;compiler assisted runtime task scheduling on a reconfigurable computer;generating high-performance custom floating-point pipelines;exploring reconfigurable architectures for explicit finite difference option pricing models;towards a viable out-of-order soft core: copy-free, checkpointed register renaming;a runtime relocation based workflow for self dynamic reconfigurable systems design;improving logic density through synthesis-inspired architecture;and replace: an incremental placement algorithm for field-programmable gate arrays.
this paper presents an analytical model that relates the architectural parameters of an FPGA to the place-and-route runtimes of the FPGA CAD tools. We consider both a simulated annealing based placement algorithm empl...
详细信息
ISBN:
(纸本)9781424438914
this paper presents an analytical model that relates the architectural parameters of an FPGA to the place-and-route runtimes of the FPGA CAD tools. We consider both a simulated annealing based placement algorithm employing a bounding-box wirelength cost function, and a negotiation-based A* router. We also show an example application of the model in early architecture evaluation.
this paper describes an approach to the placement of self-timed circuits onto commercial FPGAs, using only conventional synchronous tools available on the market. Different parts of the design are constrained in order...
详细信息
ISBN:
(纸本)9781424438914
this paper describes an approach to the placement of self-timed circuits onto commercial FPGAs, using only conventional synchronous tools available on the market. Different parts of the design are constrained in order to maintain the timing relationship required for guaranteeing the correct circuit functionality and to keep the wiring influence on system delays bounded and fixed across the different iterations. this work is part of the extension to the CodeSimulink co-design environment we made in order to allow the synthesis of asynchronous circuits from Simulink specifications.
Current trends show, it is increasingly difficult to manage the constraints of costs, power consumption, size and more than everything else, functional safety, with conventional architectures. this paper presents a ne...
详细信息
ISBN:
(纸本)9781424438914
Current trends show, it is increasingly difficult to manage the constraints of costs, power consumption, size and more than everything else, functional safety, with conventional architectures. this paper presents a new architecture to deal withthe current and upcoming requirements in safety critical applications. It proposes the use of diverse redundancy with digital and analog channels, to detect random hardware failures as well as systematic failures. that will increase the functional safety. By exploiting the ability of dynamic and partial hardware reconfiguration of FPGA and FPAA and by using the appropriate failure recovery scenario, the system availability can also be increased. Furthermore, the architecture offers the possibility to combine high accuracy with short response time.
the article presents a pipeline implementation of the block cipher CLEFIA. the article examines three known methods of implementing a single encryption round and proposes a new fourth method. the article proposes the ...
详细信息
ISBN:
(纸本)9781424438914
the article presents a pipeline implementation of the block cipher CLEFIA. the article examines three known methods of implementing a single encryption round and proposes a new fourth method. the article proposes the implementation of a key scheduler, which is highly compatible with pipeline encryption. the article contains a detailed analysis of the data processing path for the 128-bit key version of the algorithm and verifies its operation on two FPGA cards in practice. On the basis of one of these cards, the article proposes a prototype of an effective supercomputer-compatible hardware accelerator (High Performance Computing Application).
Most existing approaches to targeting high-level software to FPGAs are based on extensions to C and do not map easily to the features and characteristics of modern FPGAs. these include massive parallelism and a variet...
详细信息
ISBN:
(纸本)9781424438914
Most existing approaches to targeting high-level software to FPGAs are based on extensions to C and do not map easily to the features and characteristics of modern FPGAs. these include massive parallelism and a variety of complex IP-blocks (eg. RAMs, DSPs). In this paper we discuss a hardware implementation of SR, a software language with first class concurrency and high-level IPC. We show that the language model can be implemented efficiently on an FPGA, and that it provides a natural means to encapsulate FPGA resources. We compare against a commercial C-based synthesis tool and achieve similar resource usage using a more expressive language.
Effectively exploiting the variety of computational and storage resources available in common FPGA architectures for complex applications, such as the real-time implementation of vision algorithms, is often difficult ...
详细信息
ISBN:
(纸本)9781424438914
Effectively exploiting the variety of computational and storage resources available in common FPGA architectures for complex applications, such as the real-time implementation of vision algorithms, is often difficult in standard HDL design methodologies. Higher-level design tools can enable a design to more quickly explore a range of different architectures. In this paper we apply algorithmic C-to-FPGA synthesis technology in a structured design approach and demonstrate its added value on two relevant vision processing kernels: optical flow and debayering. the impact of the proposed approach on the design time, the FPGA resource consumption and the throughput is measured.
Power consumption in data centres is a growing issue as the cost of the power for computation and cooling has become dominant. An emerging challenge is the development of "environmentally friendly" systems. ...
详细信息
ISBN:
(纸本)9781424438914
Power consumption in data centres is a growing issue as the cost of the power for computation and cooling has become dominant. An emerging challenge is the development of "environmentally friendly" systems. In this paper we present a novel application of FPGAs for the acceleration of Information Retrieval algorithms, specifically, filtering streams/collections of documents against topic profiles. Our results show that FPGA acceleration can result in speed-ups of up to a factor 20 for large profiles.
暂无评论