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检索条件"任意字段=FPL 09: 19th International Conference on Field Programmable Logic and Applications"

共 72 条记录，以下是11-20 订阅

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SECURE FPGA TECHNOLOGIES AND TECHNIQUES

SECURE FPGA TECHNOLOGIES AND TECHNIQUES

引用

19th international conference on field programmable logic and applications

作者： Braeken, An Kubera, Serge Trouillez, Frederik Touhafi, Abdellah Mentens, Nele Vliegen, Jo Erasmushogesch Brussel Dept IWT Nijverheidskaai 170 B-1070 Anderlecht Belgium Vrije Univ Brussel B-1050 Brussels Belgium Katholieke Univ Leuven ESAD SCD CISUC Leuven Belgium Katholieke Hogesch Limburg IWT ACRO Dipenbeek Belgium

ISBN: (纸本)9781424438914

this survey paper proposes an overview of contemporary FPGA-related technologies and techniques that can be used for data and system security. As such we will give an overview of the currently available features in commonly used FPGAs and link these features to established security techniques. the main goal is to evaluate the pros and contras of the different techniques and technologies in order to give directions on the security strategy.

关键词： field programmable gate arrays (FPGA)

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INCREASING STABILITY AND DISTINGUISHABILITY OF thE DIGITAL FINGERPRINT IN FPGAS thROUGH INPUT WORD ANALYSIS

INCREASING STABILITY AND DISTINGUISHABILITY OF THE DIGITAL F...

引用

19th international conference on field programmable logic and applications

作者： Patel, Hiren Kim, Yong McDonald, J. Todd Starman, LaVern USAF AF Res Lab 1940 Allbrook Dr Wright Patterson AFB OH 45433 USA Air Force Inst Technol Wright Patterson AFB OH 45433 USA

ISBN: (纸本)9781424438914

field programmable Gate Arrays (FPGAs) have become increasingly popular in circuit development due to their rapid development times and low costs. With their increased use, the need to protect their Intellectual Property (IP) becomes more urgent. the digital fingerprint accomplishes this by creating a unique identification (ID) for each FPGA. In this research, we propose methods to dramatically increase the stability and robustness of the digital fingerprint ID by the proper choice of input sequences. We also show that by properly choosing the input word, we can significantly increase the DF resistance to operating temperature changes.

关键词： field programmable gate arrays (FPGA)

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A COMPARISON OF FPGA AND FPAA TECHNOLOGIES FOR A SIGNAL PROCESSING APPLICATION

A COMPARISON OF FPGA AND FPAA TECHNOLOGIES FOR A SIGNAL PROC...

引用

19th international conference on field programmable logic and applications

作者： Selow, Roberto Lopes, Heitor S. Erig Lima, Carlos R. Univ Posit Dept Engn Eletr Rua Prof Pedro Viriato P de Souza 5300 BR-81280330 Curitiba PR Brazil Univ Tecnol Federal Parana Dept Eletron BR-80230901 Curitiba Parana Brazil

ISBN: (纸本)9781424438914

this paper presents a comparison between two technologies for reconfigurable circuits: FPGA's and FPAA's. the comparison is based on a case study of the area of industrial control using simulations with both types of reconfigurable devices. Several design issues are discussed, including the ease of implementation, accuracy, capacity, consumption and size, among others. Based on the case study, we present qualitative directions to choose the most suitable reconfigurable device for similar applications.

关键词： field programmable gate arrays (FPGA)

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IP PROTECTION IN PARTIALLY RECONFIGURABLE FPGAS

IP PROTECTION IN PARTIALLY RECONFIGURABLE FPGAS

引用

19th international conference on field programmable logic and applications

作者： Kepa, Krzysztof Morgan, Fearghal Kosciuszkiewicz, Krzysztof Natl Univ Ireland Dept Elect Engn Galway Ireland

ISBN: (纸本)9781424438914

As FPGA technology and related EDA tools develop, design IP protection and licensing requires increasing consideration. the current multi-player, Partial-Reconfiguration (PR) design flow does not facilitate bitstream-level IP core license enforcement, e.g, time-limited or pay-per-use. this paper proposes the use of a Secure Reconfigurable Controller (SeReCon) for accounting of IP core usage, e.g. total runtime, no. of activations etc, in a PR system. this paper extends the reported SeReCon root-of-trust to support license enforcement within the PR flow and to facilitate confidentiality of the IP core during the PR system life-cycle. A prototype IP-aware SeReCon demonstrator, implemented on Virtex-5 and supporting reconfiguration of a PCIe accelerator with cryptographic IP cores is described.

关键词： field programmable gate arrays (FPGA)

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HIGH SPEED FIXED POINT DIVIDERS FOR FPGAS

HIGH SPEED FIXED POINT DIVIDERS FOR FPGAS

引用

19th international conference on field programmable logic and applications

作者： Sutter, Gustavo Deschamps, Jean-Pierre Univ Autonoma Madrid Madrid Spain Univ Rovira & Virgili Tarragona Spain

ISBN: (纸本)9781424438914

this paper presents a novel class of division algorithm that reduces the delay of calculus introducing more concurrency in computation. the algorithm is suitable for fixed-point operands and divides in a radix r = 2(k), producing k bits at each iteration. the proposed digit recurrence algorithm has two different architectures, a first one for general hardware implementation, and the second one optimized for configurable logic. Results show a speedup greater to three times respect to a classical non-restoring division implemented in Xilinx Devices. the dividers were also compared against Xilinx CoreGenerator circuits clearly outperforming latency and area

关键词： field programmable gate arrays (FPGA)

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DPA RESISTANCE FOR LIGHT-WEIGHT IMPLEMENTATIONS OF CRYPTOGRAPHIC ALGORIthMS ON FPGAS

DPA RESISTANCE FOR LIGHT-WEIGHT IMPLEMENTATIONS OF CRYPTOGRA...

引用

19th international conference on field programmable logic and applications

作者： Velegalati, Rajesh Kaps, Jens-Peter George Mason Univ Volgenau Sch IT&E Fairfax VA 22030 USA

ISBN: (纸本)9781424438914

Recent advances in field programmable Gate Array (FPGA) technology are bound to make FPGAs a popular platform for battery powered devices. Many applications of such devices are mission critical and require the use of cryptographic algorithms to provide the desired security. However, Differential Power Analysis (DPA) attacks pose a sever threat against otherwise secure cryptographic implementations. Current techniques to defend against DPA attacks such as Dynamic Differential logic (DDL) lead to an increase in area consumption of factor five or more. In this paper we show that moderate security against DPA attacks can be achieved for FPGAs using DDL resulting in an area increase of not much more than a factor two over standard FPGA implementations. Our design flow requires only FPGA design tools and some scripts.

关键词： field programmable gate arrays (FPGA)

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RANDOM NUMBERS GENERATION: INVESTIGATION OF NARROW TRANSITIONS SUPPRESSION ON FPGA

RANDOM NUMBERS GENERATION: INVESTIGATION OF NARROW TRANSITIO...

引用

19th international conference on field programmable logic and applications

作者： Rozic, Vladimir Verbauwhede, Ingrid Katholieke Univ Leuven ESAT SCD COSIC & IBBT B-3001 Louvain Belgium

ISBN: (纸本)9781424438914

Random number generators play an important role in the field of cryptography and security. It is often required that a random number generator consists of digital logic blocks only, so that it can be implemented on reconfigurable platforms. Since randomness cannot be proved by statistical tests there is a need for a provably secure hardware random number generator. In order to provide a proof of security, an experimental investigation of various physical effects on reconfigurable platforms is needed. In this paper we focus on the effect of narrow transitions suppression in the logic gates. the estimation of this effect may be crucial for the validity of the security proof of a RNG design. We explain our views on how experiments on FPGA should be performed and we give description of the measurement setup. We show that up to 98% of the transitions are suppressed in our experimental FPGA setup.

关键词： field programmable gate arrays (FPGA)

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A LOW COST RECONFIGURABLE SOFT PROCESSOR FOR MULTIMEDIA applications: DESIGN SYNthESIS AND PROGRAMMING MODEL

A LOW COST RECONFIGURABLE SOFT PROCESSOR FOR MULTIMEDIA APPL...

引用

19th international conference on field programmable logic and applications

作者： Chalamalasetti, Sai Rahul Vanderbauwhede, Wim Purohit, Sohan Margala, Martin Univ Massachusetts Lowell MA USA Univ Glasgow Dept Comp Sci Glasgow G12 8QQ Lanark Scotland

ISBN: (纸本)9781424438914

this paper presents an FPGA implementation of a low cost 8bit reconfigurable processor core for media processing applications. the core is optimized to provide all basic arithmetic and logic functions required by the media processing and other domains, as well as to make it easily integrable into a 2D array. this paper presents an investigation of the feasibility of the core as a potential soft processing architecture for FPGA platforms. the core was synthesized on the entire Virtex FPGA family to evaluate its overall performance, scalability and portability. A special feature of the proposed architecture is its simple programming model which allows low level programming. throughput results for popular benchmarks coded using the programming model and cycle accurate simulator are presented.

关键词： field programmable gate arrays (FPGA)

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sFPGA2-A SCALABLE GALS FPGA ARCHITECTURE AND DESIGN MEthODOLOGY

sFPGA2-A SCALABLE GALS FPGA ARCHITECTURE AND DESIGN METHODOL...

引用

19th international conference on field programmable logic and applications

作者： Syed, Rizwan Chen, Xiaolei Ha, Yajun Veeravalli, Bharadwaj Natl Univ Singapore Dept Elect & Comp Engn Singapore 117576 Singapore

ISBN: (纸本)9781424438914

the interconnection networks used by current fine grain FPGAs are not scalable for very big array sizes. To address this issue, we apply the GALS (Globally Asynchronous and Locally Synchronous) paradigm to build scalable FPGAs. the logic resources are divided into locally synchronous tiles and asynchronous communications among different tiles. To route the asynchronous communications, we build a serial network-on-chip. Targeting streaming applications, we propose a design flow that maps user applications to our new FPGA architecture. To validate our architecture and design flow, we build an emulation prototype and develop a JPEG baseline encoder as the case study. We have successfully demonstrated the concept and predict a maximum frequency of 224MHz for designs mapping to sFPGA2 architecture.

关键词： field programmable gate arrays (FPGA)

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GENERATING HIGH-PERFORMANCE CUSTOM FLOATING-POINT PIPELINES

GENERATING HIGH-PERFORMANCE CUSTOM FLOATING-POINT PIPELINES

引用

19th international conference on field programmable logic and applications

作者： de Dinechin, Florent Klein, Cristian Pasca, Bogdan Univ Lyon LIP CNRS INRIA ENSLyon UCBL Ecole Normale Super Lyon F-69364 Lyon France

ISBN: (纸本)9781424438914

Custom operators, working at custom precisions, are a key ingredient to fully exploit the FPGA flexibility advantage for high-performance computing. Unfortunately, such operators are costly to design, and application designers tend to rely on less efficient off-the-shelf operators. To address this issue, an open-source architecture generator framework is introduced. Its salient features are an easy learning curve from VHDL, the ability to embed arbitrary synthesizable VHDL code, portability to mainstream FPGA targets from Xilinx and Altera, automatic management of complex pipelines with support for frequency-directed pipeline, and automatic test-bench generation. this generator is presented around the simple example of a collision detector, which it significantly improves in accuracy, DSP count, logic usage, frequency and latency with respect to an implementation using standard floating-point operators.

关键词： field programmable gate arrays (FPGA)

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