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检索条件"任意字段=FPL 09: 19th International Conference on Field Programmable Logic and Applications"

共 72 条记录，以下是51-60 订阅

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IMPROVING logic DENSITY thROUGH SYNthESIS-INSPIRED ARCHITECTURE

IMPROVING LOGIC DENSITY THROUGH SYNTHESIS-INSPIRED ARCHITECT...

引用

19th international conference on field programmable logic and applications

作者： Anderson, Jason H. Wang, Qiang Univ Toronto Dept ECE Toronto ON Canada Xilinx Inc San Jose CA USA

ISBN: (纸本)9781424438914

We leverage properties of the logic synthesis netlist to define both a logic element architecture and an associated technology mapping algorithm that together provide improved logic density. We demonstrate that an "extended" logic element with slightly modified K-input LUTs achieves much of the benefit of an architecture with K+1-input LUTs, while consuming silicon area close to a K-LUT (a K-LUT requires half the area of a K+1-LUT). We introduce the notion of "non-inverting paths" in a circuit's AND-inverter graph (AIG) and show their utility in mapping into the proposed logic element. Results show that while circuits mapped to a traditional 5-LUT architecture need 14% more LUTs and have 12% more depth than a 6-LUT architecture, our extended 5-LUT architecture requires only 7% more LUTs and 2.5% more depth than 6-LUTs, on average. Nearly all of the depth reduction associated with moving from K-input to K+1-input LUTs can be achieved with considerably less area using extended K-LUTs. We further show that 6-LUT optimal mapping depths can be achieved with a small fraction of the LUTs in hardware being 6-LUTs and the remainder being extended 5-LUTs, suggesting that a heterogeneous logic block architecture may prove to be advantageous.

关键词： Computer circuits

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An FPGA based Verification Platform for HyperTransport 3.x

An FPGA based Verification Platform for HyperTransport 3.x

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19th international conference on field programmable logic and applications

作者： Litz, Heiner Froening, Holger thuermer, Maximilian Bruening, Ulrich Univ Heidelberg Comp Architecture Grp D-6900 Heidelberg Germany

ISBN: (纸本)9781424438914

In this paper we present a verification platform designed for Hyper Transport 3.x (HT3) applications. Hyper Transport 3.x is a very low latency and high bandwidth chip-to-chip interconnect which is particularly used in AMDs novel Opteron processor series. As it is an open protocol, a broad application range exists ranging from southbridge chips over closely coupled accelerators to add in cards. Its main advantage over PCI-Express is that it allows direct connection to the CPU resulting in significantly improved latency performance. To enable the development of new Hyper Transport products we herein present the very first FPGA based prototyping platform for HT3.x. Such a platform is enormously valuable as new designs can be tested in real world systems before producing an costly application specific integrated circuit (ASIC). Due to the high operating frequencies of HT3.x an FPGA based solution is extremely challenging as we will describe in this paper. Our presented architecture is evaluated and implemented in the form of a printed circuit board (PCB). this add-in card represents the world's first available HyperTransport 3 device. Early adopters of HT3 benefit from the results of this work for rapid prototyping and Hardware/Software co-verification of new HT3 designs and products.

关键词： field programmable gate arrays (FPGA)

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SVM SPEAKER VERIFICATION SYSTEM BASED ON A LOW-COST FPGA

SVM SPEAKER VERIFICATION SYSTEM BASED ON A LOW-COST FPGA

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19th international conference on field programmable logic and applications

作者： Ramos-Lara, Rafael Lopez-Garcia, Mariano Canto-Navarro, Enrique Puente-Rodriguez, Luis Tech Univ Catalonia Vilanova I La Geltru 08800 Spain Univ Carlos III Madrid E-28903 Getafe Spain

ISBN: (纸本)9781424438914

Biometric systems, characterized by their high confidential levels of security, are usually based on high-performance microprocessors implemented on personal computers. these advanced devices contain floating-point units able to carry out millions of operations per second at frequencies in the GHz range, being qualified to resolve the most complex algorithms in just a few hundred of milliseconds. However, their main drawback is the cost, and the necessary space required to incorporate their external associated peripherals. this disadvantage is especially significant in the low-cost consumer market, where factors such as price and size determine the viability of a product. the use of an FPGA is a suited way to implement systems that require a high computational capability at affordable prices. Besides, these devices allow the design of complex digital systems with outstanding performances in terms of execution times. this paper presents the implementation of a SVM (Support Vector Machines) speaker verification system on a low-cost FPGA. Experimental results show as our system is able to verify a person's identity as fast as a high-performance microprocessor based on a Pentium IV personal computer.

关键词： field programmable gate arrays (FPGA)

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TOWARDS A UNIQUE FPGA-BASED IDENTIFICATION CIRCUIT USING PROCESS VARIATIONS

TOWARDS A UNIQUE FPGA-BASED IDENTIFICATION CIRCUIT USING PRO...

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19th international conference on field programmable logic and applications

作者： Yu, H. Leong, P. H. W. Hinkelmann, H. Moller, L. Glesner, M. Zipf, P. Chinese Univ Hong Kong Dept Comp Sci & Engn Hong Kong Hong Kong Peoples R China Tech Univ Darmstadt Inst Microelect Syst Darmstadt Germany Univ Kassel Digital Technol Lab Kassel Germany

ISBN: (纸本)9781424438914

A compact chip identification (ID) circuit with improved reliability is presented. Ring oscillators are used to measure the spatial process variation and the ID is based on their relative speeds. A novel averaging and postprocessing scheme is employed to accurately determine the faster of two similar-frequency ring oscillators in the presence of noise. Using this scheme, the average number of unstable bits i.e. bits which can change in value between readings, measured on an FPGA is shown to be reduced from 5.3% to 0.9% at 20 degrees C. Within the range 20 - 60 degrees C, the percentage of unstable bits is within 2.8%. An analysis of the effectiveness of the scheme and the distribution of the errors is given over different temperature ranges and FPGA chips.

关键词： field programmable gate arrays (FPGA)

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HARDWARE IMPLEMENTATION OF MPI_BARRIER ON AN FPGA CLUSTER

HARDWARE IMPLEMENTATION OF MPI_BARRIER ON AN FPGA CLUSTER

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19th international conference on field programmable logic and applications

作者： Gao, Shanyuan Schmidt, Andrew G. Sass, Ron Univ N Carolina Dept Elect & Comp Engn Reconfigurable Comp Syst Lab Charlotte NC 28223 USA

ISBN: (纸本)9781424438914

Message-Passing is the dominant programming model for distributed memory parallel computers and Message-Passing Interface (MPI) is the standard. Along with point-to-point send and receive message primitives, MPI includes a set of collective communication operations that are used to synchronize and coordinate groups of tasks. the MPI_Barrier, one of the most important collective procedures, has been extensively studied on a variety of architectures over last twenty years. However, a cluster of Platform FPGAs is a new architecture and offers interesting, resource-efficient options for implementing the barrier operation. this paper describes an FPGA implementation of MPI_Barrier. the premise is that barrier (and other collective communication operations) are very sensitive to latency as the number of nodes scales to the tens-of-thousands. the relatively slow processors found on FPGAs will significantly cap performance. the FPGA hardware design implements a tree-based algorithm and is tightly integrated with the custom high-speed on-chip/off-chip network. MPI access is available through a specially-designed kernel module. this effectively offloads the work from the CPU and OS into hardware. the evaluation of this design shows signficant performance gains compared with a conventional software implementation on both an FPGA cluster and a commodity cluster. Further, it suggests that moving other MPI collective operations into hardware would be beneficial.

关键词： field programmable gate arrays (FPGA)

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the Monte Carlo PUF 27

The Monte Carlo PUF

引用

27th international conference on field programmable logic and applications (fpl)

作者： Rozic, Vladimir Yang, Bohan Vliegen, Jo Mentens, Nele Verbauwhede, Ingrid Katholieke Univ Leuven COSIC Kasteelpk Arenberg 10 B-3001 Leuven Heverlee Belgium

ISBN: (纸本)9789090304281

Physically unclonable functions are used for IP protection, hardware authentication and supply chain security. While many PUF constructions have been put forward in the past decade, only few of them are applicable to FPGA platforms. Strict constraints on the placement and routing are the main disadvantages of the existing PUFs on FPGAs, because they place a high effort on the designer. In this paper we propose a new delay-based PUF construction called Monte Carlo PUF, that does not require low-level placement and routing control. this construction relies on the on-chip Monte Carlo method that is applied for measuring the delays of logic elements in order to extract a unique device fingerprint. the proposed construction allows a trade-off between the evaluation time and the error rate. the Monte Carlo PUF is implemented and evaluated on Xilinx Spartan-6 FPGAs.

关键词： Monte Carlo methods Delays field programmable gate arrays Delay lines Radiation detectors Ring oscillators Security

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DATA PARALLEL FPGA WORKLOADS: SOFTWARE VERSUS HARDWARE

DATA PARALLEL FPGA WORKLOADS: SOFTWARE VERSUS HARDWARE

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19th international conference on field programmable logic and applications

作者： Yiannacouras, Peter Steffan, J. Gregory Rose, Jonathan Univ Toronto Edward S Rogers Sr Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9781424438914

Commercial soft processors are unable to effectively exploit the data parallelism present in many embedded systems workloads, requiring FPGA designers to exploit it (laboriously) with manual hardware design. Recent research [1, 2] has demonstrated that soft processors augmented with support for vector instructions provide significant improvements in performance and scalability for data-parallel workloads. these soft vector processors provide a software environment for quickly encoding data parallel computation, but their competitiveness with manual hardware design in terms of area and performance remains unknown. In this work, using an FPGA platform equipped with DDR memory executing data-parallel EEMBC embedded benchmarks, we measure the area/performance gaps between (i) a scalar soft processor, (ii) our improved soft vector processor, and (iii) custom FPGA hardware. We demonstrate that the 432x wall clock performance gap between scalar executed C and custom hardware can be reduced significantly to 17x using our improved soft vector processor, while silicon-efficiency is improved by 3x in terms of area-delay product. We modified the architecture to mitigate three key advantages we observed in custom hardware: loop overhead, data delivery, and exact resource usage. Combined these improvements increase performance by 3x and reduce area by almost half, significantly reducing the need for designers to resort to more challenging custom hardware implementations.

关键词： field programmable gate arrays (FPGA)

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DT-CGRA: Dual-Track Coarse-Grained Reconfigurable Architecture for Stream applications 26

DT-CGRA: Dual-Track Coarse-Grained Reconfigurable Architectu...

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26th international conference on field-programmable logic and applications (fpl)

作者： Fan, Xitian Li, Huimin Cao, Wei Wang, Lingli Fudan Univ State Key Lab ASIC & Syst 825 Zhangheng Rd Shanghai 201203 Peoples R China

ISBN: (纸本)9782839918442

this paper presents a new type of coarse-grained reconfigurable architecture (CGRA) for the object inference domain in machine learning. the proposed CGRA is optimized for stream processing and a correspondent programming model called dual-track model is proposed. the CGRA is realized in Verilog HDL and implemented in SMIC 55 nm process, with the footprint of 3.79 mm(2) and consuming 1.79 W at 500 MHz. To evaluate the performance, eight machine-learning algorithms including HOG, CNN, k-means, PCA, SPM, linear-SVM, Softmax and Joint-Bayesian are selected as benchmarks. these algorithms cover a general machine learning flow in object inference domain: feature extraction, feature selection and inference. the experimental results show that the proposed CGRA can gain 1443x average energy efficiency comparing to the Intel i7-3770 CPU and 7.82x energy efficiency comparing to a high performance FPGA solution [19].

关键词： coarse-grained reconfigurable architecture domain-specific computing machine learning object inference

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A Self-Calibrating True Random Number Generator 29

A Self-Calibrating True Random Number Generator

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29th international conference on field-programmable logic and applications (fpl)

作者： Peetermans, Adriaan Grujic, Milos Rozic, Vladimir Verbauwhede, Ingrid Katholieke Univ Leuven Imec COSIC Kasteelpk Arenberg 10 B-3001 Leuven Belgium

ISBN: (纸本)9781728148847

True Random Number Generators (TRNGs) are essential in all security systems. Unfortunately, large design effort is required to ensure that a TRNG design on a fieldprogrammable Gate Array (FPGA) generates a sufficient entropy density at its output. this design effort relates to the fact that for each FPGA family a manual placement and routing procedure has to be executed. On top of this often comes the additional effort of finding a suitable location inside the target FPGA. this searching procedure has to be repeated for every device separately. In this demo, we show the working of a novel entropy source for the Coherent Sampling Ring Oscillator (COSO) based TRNG. this entropy source eliminates the need for any manual intervention during the implementation process. It generates two oscillating signals that can be matched with a precision of a few picoseconds. A controller regulates this entropy source based on some predefined bounds on the period length difference of the two oscillating signals.

关键词： field programmable gate arrays Generators Entropy Graphical user interfaces Monitoring Manuals Ring oscillators

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A High -Performance Out -of-Order Soft Processor Without Register Renaming 30

A High -Performance Out -of-Order Soft Processor Without Reg...

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30th international conference on field-programmable logic and applications (fpl)

作者： Mitsuno, Satoshi Kadomoto, Junichiro Koizumi, Toru Shioya, Ryota Irie, Hidetsugu Sakai, Shuichi Univ Tokyo Tokyo Japan

ISBN: (纸本)9781728199023

Owing to the growth of FPGA-based systems and the increasing complexity of applications, the demand for highperformance soft processors in FPGAs has increased. the performance of processors is enhanced through out-of-order (000) superscalar execution using a register renaming mechanism. However, the register renaming mechanism has two problems. First, it requires a register mapping table (RMT), which usually comprises a RAM with a large number of ports. A multi-port RAM is not suitable for an FPGA. Second, register renaming complicates recovery mechanisms for exceptions, such as branch mispredictions. these problems increase the usage of resources and hinder the improvement of performance. Recently, the STRAIGHT architecture was proposed to solve these problems. STRAIGHT has a unique instruction format and enables OoO execution without register renaming. this approach eliminates the RMT and makes the recovery operation more efficient. In this study, we demonstrate a high-performance OoO STRAIGHT soft processor by implementing several mechanisms for adopting the STRAIGHT architecture and fabricate the first STRAIGHT processor capable of executing practical complex programs. Compared to a state-of-the-art OoO soft processor, our processor consumes approximately 17% fewer LUTs and 10% fewer FlipFlops and achieves 15% higher performance in CoreMark, which is a standard benchmark.

关键词： field programmable gate arrays (FPGA)

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