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检索条件"任意字段=FPL 09: 19th International Conference on Field Programmable Logic and Applications"
72 条 记 录,以下是61-70 订阅
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Automated Extra Pipeline Analysis of applications mapped to Xilinx UltraScale plus FPGAs  26
Automated Extra Pipeline Analysis of Applications mapped to ...
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26th international conference on field-programmable logic and applications (fpl)
作者: Ganusov, Ilya Fraisse, Henri Ng, Aaron Possignolo, Rafael Trapani Das, Sabya Xilinx Inc 2100 Log Dr San Jose CA 95124 USA Univ Calif Santa Cruz Dept Comp Engn Santa Cruz CA 95064 USA
this paper describes the methodology and algorithms behind extra pipeline analysis tools released in the Xilinx Vivado Design Suite version 2015.3. Extra pipelining is one of the most effective ways to improve perform... 详细信息
来源: 评论
POWER EFFICIENT DSP DATAPAth CONFIGURATION MEthODOLOGY FOR FPGA
POWER EFFICIENT DSP DATAPATH CONFIGURATION METHODOLOGY FOR F...
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18th international conference on field programmable and logic applications
作者: McKeown, S. Woods, R. McAllister, J. Queens Univ Belfast Programmable Syst Lab Inst Elect Commun & Informat Technol Belfast BT3 9DT Antrim North Ireland
Exploiting the underutilisation of variable-length DSP algorithms during normal operation is vital, when seeking to maximise the achievable functionality of an application within peak power budget. A system level, low... 详细信息
来源: 评论
Improving timing-driven FPGA packing with physical information
Improving timing-driven FPGA packing with physical informati...
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17th international conference on field programmable logic and applications
作者: Chen, Doris T. Vorwerk, Kristofer Kennings, Andrew Univ Waterloo Waterloo ON N2L 3G1 Canada
the traditional approach to FPGA packing and CLB-level placement has been shown to yield significantly worse quality than approaches which allow BLES to move during placement. In practice, however, modern FPGA archite... 详细信息
来源: 评论
MacroMap: A Technology Mapping Algorithm for Heterogeneous FPGAs with Effective Area Estimation
MacroMap: A Technology Mapping Algorithm for Heterogeneous F...
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18th international conference on field programmable and logic applications
作者: Wei, Xing Chen, Juanjuan Zhou, Qiang Cai, Yici Bian, Jinian Hong, Xianlong Tsinghua Univ Dept Comp Sci & Technol Tsinghua Natl Lab Informat Sci & Technol Beijing 100084 Peoples R China
Recent generation of FPGA devices takes advantage of speed and density benefits resulted from heterogeneous FPGA architecture, in which several basic LUTs can be combined to form one larger size LUT called Macro. Larg... 详细信息
来源: 评论
A cost-effective technique for mapping BLUTs to QLUTs in FPGAs
A cost-effective technique for mapping BLUTs to QLUTs in FPG...
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20th international conference on field programmable logic and applications, fpl 2010
作者: Ritt, Marcus Lisboa, Carlos Arthur Lang Carro, Luigi Lazzari, Cristiano Instituto de Informática PPGC - UFRGS Brazil ALGOS - INESC-ID Portugal
Quaternary logic has shown to be a promising alternative for implementing FPGAs, since voltage mode quaternary circuits can reduce the circuits' cost and at the same time reduce its power consumption. In this pape... 详细信息
来源: 评论
L4: An FPGA-based accelerator for detailed maze routing
L4: An FPGA-based accelerator for detailed maze routing
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17th international conference on field programmable logic and applications
作者: Nestor, John A. Lavine, JeremY Lafayette Coll ECE Dept Easton PA 18042 USA
this paper describes an FPGA-based accelerator for maze routing applications such as integrated circuit detailed routing. the accelerator efficiently supports multiple layers, multi-terminal nets, and rip up and rerou... 详细信息
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Self-testing of linear segments in user-programmed FPGAs  10th
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10th international conference on field-programmable logic and applications, fpl 2000
作者: Tomaszewicz, Pawel Warsaw University of Technology Nowowiejska 15/19 Warsaw00-665 Poland
A method for the development of a test plan for BIST-based exhaustive testing of a circuit implemented with an in-system reconfigurable FPGA is presented. A test plan for application-dependent testing of an FPGA is ba... 详细信息
来源: 评论
Exploiting reconfigurability for effective detection of delay faults in LUT-based FPGAs  10th
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10th international conference on field-programmable logic and applications, fpl 2000
作者: Krasniewski, Andrzej Institute of Telecommunications Warsaw University of Technology Nowowiejska 15/19 Warsaw00-665 Poland
We present an extension of a procedure for self-testing of an FPGA that implements a user-defined function. this extension, intended to improve the detectability of FPGA delay faults, exploits the reconfigurability of... 详细信息
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Fast carrier and phase synchronization units for digital receivers based on re-configurable logic
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10th international conference on field-programmable logic and applications, fpl 2000
作者: Blaickner, A. Nagy, O. Grünbacher, H. Carinthia Tech Institute-CTI Richard-Wagner-Strasse 19 VillachA-9500 Austria
Wireless communication systems operate within a wide variety of dynamic ranges, variable bandwidths and carrier frequencies. New high density re-programmable logic arrays are a suitable technology basis providing suff... 详细信息
来源: 评论
DT-CGRA: Dual-track coarse-grained reconfigurable architecture for stream applications
DT-CGRA: Dual-track coarse-grained reconfigurable architectu...
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international conference on field programmable logic and applications
作者: Xitian Fan Huimin Li Wei Cao Lingli Wang State Key Laboratory of ASIC and System Fudan University Shanghai China
this paper presents a new type of coarse-grained reconfigurable architecture (CGRA) for the object inference domain in machine learning. the proposed CGRA is optimized for stream processing and a correspondent program... 详细信息
来源: 评论