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检索条件"任意字段=FPL 09: 19th International Conference on Field Programmable Logic and Applications"

共 72 条记录，以下是61-70 订阅

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Automated Extra Pipeline Analysis of applications mapped to Xilinx UltraScale plus FPGAs 26

Automated Extra Pipeline Analysis of Applications mapped to ...

引用

26th international conference on field-programmable logic and applications (fpl)

作者： Ganusov, Ilya Fraisse, Henri Ng, Aaron Possignolo, Rafael Trapani Das, Sabya Xilinx Inc 2100 Log Dr San Jose CA 95124 USA Univ Calif Santa Cruz Dept Comp Engn Santa Cruz CA 95064 USA

ISBN: (纸本)9782839918442

this paper describes the methodology and algorithms behind extra pipeline analysis tools released in the Xilinx Vivado Design Suite version 2015.3. Extra pipelining is one of the most effective ways to improve performance of FPGA applications. Manual pipelining, however, often requires significant efforts from FPGA designers who need to explore various changes in the RTL and re-run the flow iteratively. the automatic pipelining approach described in this paper, in contrast, allows FPGA users to explore latency vs. performance trade-offs of their designs before investing time and effort into modifying RTL. We describe algorithms behind these tools which use simple cut heuristics to maximize performance improvement while minimizing additional latency and register overhead. To demonstrate the effectiveness of the proposed approach, we analyse a set of 93 commercial FPGA applications and IP blocks mapped to Xilinx UltraScale+ and UltraScale generations of FPGAs. the results show that extra pipelining can provide from 18% to 29% potential Fmax improvement on average. It also shows that the distribution of improvements is bimodal, with almost half of benchmark suite designs showing no improvement due to the presence of large loops. Finally, we demonstrate that highly-pipelined designs map well to UltraScale+ and UltraScale FPGA architectures. Our approach demonstrates 19% and 20% Fmax improvement potential for the UltraScale+ and UltraScale architectures respectively, with the majority of applications reaching their loop limit through pipelining.

关键词： field programmable gate arrays (FPGA)

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POWER EFFICIENT DSP DATAPAth CONFIGURATION MEthODOLOGY FOR FPGA

POWER EFFICIENT DSP DATAPATH CONFIGURATION METHODOLOGY FOR F...

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18th international conference on field programmable and logic applications

作者： McKeown, S. Woods, R. McAllister, J. Queens Univ Belfast Programmable Syst Lab Inst Elect Commun & Informat Technol Belfast BT3 9DT Antrim North Ireland

ISBN: (纸本)9781424419609

Exploiting the underutilisation of variable-length DSP algorithms during normal operation is vital, when seeking to maximise the achievable functionality of an application within peak power budget. A system level, low power design methodology for FPGA-based, variable length DSP IP cores is presented. Algorithmic commonality is identified and resources mapped with a configurable datapath, to increase achievable functionality. It is applied to a digital receiver application where a 100% increase in operational capacity is achieved in certain modes without significant power or area budget increases. Measured results show resulting architectures requires 19% less peak power, 33% fewer multipliers and 12% fewer slices than existing architectures.

关键词： field programmable gate arrays (FPGA)

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Improving timing-driven FPGA packing with physical information

Improving timing-driven FPGA packing with physical informati...

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17th international conference on field programmable logic and applications

作者： Chen, Doris T. Vorwerk, Kristofer Kennings, Andrew Univ Waterloo Waterloo ON N2L 3G1 Canada

ISBN: (纸本)9781424410590

the traditional approach to FPGA packing and CLB-level placement has been shown to yield significantly worse quality than approaches which allow BLES to move during placement. In practice, however, modern FPGA architectures require expensive DRC checks which can render full BLE-level placement impractical. We address this problem by proposing a novel clustering framework that uses physical information to produce better initial packings which can, in turn, reduce the amount Of BLE-level placement that is required. We quantify our packing technique across accepted benchmarks and show that it produces results with 16% less wire length, 19% smaller minimum channel widths, and 8% less critical path delay, on average, than leading methods.

关键词： field programmable gate arrays (FPGA)

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MacroMap: A Technology Mapping Algorithm for Heterogeneous FPGAs with Effective Area Estimation

MacroMap: A Technology Mapping Algorithm for Heterogeneous F...

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18th international conference on field programmable and logic applications

作者： Wei, Xing Chen, Juanjuan Zhou, Qiang Cai, Yici Bian, Jinian Hong, Xianlong Tsinghua Univ Dept Comp Sci & Technol Tsinghua Natl Lab Informat Sci & Technol Beijing 100084 Peoples R China

ISBN: (纸本)9781424419609

Recent generation of FPGA devices takes advantage of speed and density benefits resulted from heterogeneous FPGA architecture, in which several basic LUTs can be combined to form one larger size LUT called Macro. Large Macros not only decrease network depth efficiently but also reduce area. In this paper, a new technology mapping algorithm, named MacroMap is proposed for the heterogeneous FPGAs with effective area estimation to overcome the main disadvantage that traditional technology mapping algorithms only generate one kind of typical K-LUT and cannot make full use of LUTs with different sizes (basic LUTs and Macros). Experimental results show that MacroMap can obtain 19% gain on area while keeping the network depth optimal compared with the existing heterogeneous FPGA mapping algorithm heteromap([8]).

关键词： field programmable gate arrays (FPGA)

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A cost-effective technique for mapping BLUTs to QLUTs in FPGAs

A cost-effective technique for mapping BLUTs to QLUTs in FPG...

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20th international conference on field programmable logic and applications, fpl 2010

作者： Ritt, Marcus Lisboa, Carlos Arthur Lang Carro, Luigi Lazzari, Cristiano Instituto de Informática PPGC - UFRGS Brazil ALGOS - INESC-ID Portugal

ISBN: (纸本)9780769541792

Quaternary logic has shown to be a promising alternative for implementing FPGAs, since voltage mode quaternary circuits can reduce the circuits' cost and at the same time reduce its power consumption. In this paper, we study the implementation of circuits in quaternary logic. To obtain cost-effective implementations of quaternary circuits, we propose a mapping from binary to quaternary circuits based on integer linear programming. Our results show that the expected improvements can be achieved, reducing, in average, the number of transistors by 27% and the number of nets by 19%, compared to a binary implementation. © 2010 IEEE.

关键词： field programmable gate arrays (FPGA)

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L4: An FPGA-based accelerator for detailed maze routing

L4: An FPGA-based accelerator for detailed maze routing

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17th international conference on field programmable logic and applications

作者： Nestor, John A. Lavine, JeremY Lafayette Coll ECE Dept Easton PA 18042 USA

ISBN: (纸本)9781424410590

this paper describes an FPGA-based accelerator for maze routing applications such as integrated circuit detailed routing. the accelerator efficiently supports multiple layers, multi-terminal nets, and rip up and reroute. By time-multiplexing multiple layers over a two-dimensional array of processing elements, this approach can support multi-layer grids large enough for detailed routing while providing at 1-2 orders of magnitude speedup over software running on a modern desktop computer. the current implementation supports a 32 X 32 routing grid with up to 16 layers in a single Xilinx XC2V6000 FPGA. Up to 64 X 64 routing grids are feasible in larger commercially available FPGAs. Performance measurements (including interface overhead) show a speedup of 29X-93X over the classic Lee Algorithm and 5X-19X over the A* Algorithm. An improved interface design could yield significantly larger speedups.

关键词： field programmable gate arrays (FPGA)

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Self-testing of linear segments in user-programmed FPGAs 10th

引用

10th international conference on field-programmable logic and applications, fpl 2000

作者： Tomaszewicz, Pawel Warsaw University of Technology Nowowiejska 15/19 Warsaw00-665 Poland

ISBN: (纸本)3540678999

A method for the development of a test plan for BIST-based exhaustive testing of a circuit implemented with an in-system reconfigurable FPGA is presented. A test plan for application-dependent testing of an FPGA is based on the concept of a logic cone and linear segment. Linear segments that satisfy single- or multi-generator compatibility requirement can be combinationally exhaustively tested concurrently and are merged into a test block. Two methods for merging logic cones and linear segments are proposed. Experimental results are presented. © Springer-Verlag Berlin Heidelberg 2000.

关键词： field programmable gate arrays (FPGA)

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Exploiting reconfigurability for effective detection of delay faults in LUT-based FPGAs 10th

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10th international conference on field-programmable logic and applications, fpl 2000

作者： Krasniewski, Andrzej Institute of Telecommunications Warsaw University of Technology Nowowiejska 15/19 Warsaw00-665 Poland

ISBN: (纸本)3540678999

We present an extension of a procedure for self-testing of an FPGA that implements a user-defined function. this extension, intended to improve the detectability of FPGA delay faults, exploits the reconfigurability of FPGAs and is based on modifying the functions of LUTs in the section under test. A modification procedure replaces a user-defined function of each LUT with a specific function that preserves the blocking capability and input-output transition pattern of the original function. We show that the proposed method significantly increases the susceptibility of FPGA delay faults to random testing. © Springer-Verlag Berlin Heidelberg 2000.

关键词： field programmable gate arrays (FPGA)

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Fast carrier and phase synchronization units for digital receivers based on re-configurable logic

引用

10th international conference on field-programmable logic and applications, fpl 2000

作者： Blaickner, A. Nagy, O. Grünbacher, H. Carinthia Tech Institute-CTI Richard-Wagner-Strasse 19 VillachA-9500 Austria

ISBN: (纸本)3540678999

Wireless communication systems operate within a wide variety of dynamic ranges, variable bandwidths and carrier frequencies. New high density re-programmable logic arrays are a suitable technology basis providing sufficient processing power required by software radio concepts employing multiple standards and transmission schemes. For high speed wireless data transmission and access networks as used in multimedia communication systems fast signal synchronization and acquisition schemes are required. Within this work, programmable carrier phase synchronization units have been designed as FPGA based subsystems to be used in various re-configurable digital receiver concepts. the performance and the available processing capacity was investigated and verified within a rapid prototyping design flow environment. © Springer-Verlag Berlin Heidelberg 2000.

关键词： Software radio

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DT-CGRA: Dual-track coarse-grained reconfigurable architecture for stream applications

DT-CGRA: Dual-track coarse-grained reconfigurable architectu...

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international conference on field programmable logic and applications

作者： Xitian Fan Huimin Li Wei Cao Lingli Wang State Key Laboratory of ASIC and System Fudan University Shanghai China

this paper presents a new type of coarse-grained reconfigurable architecture (CGRA) for the object inference domain in machine learning. the proposed CGRA is optimized for stream processing and a correspondent programming model called dual-track model is proposed. the CGRA is realized in Verilog HDL and implemented in SMIC 55 nm process, with the footprint of 3.79 mm 2 and consuming 1.79 W at 500 MHz. To evaluate the performance, eight machine-learning algorithms including HOG, CNN, k-means, PCA, SPM, linear-SVM, Softmax and Joint-Bayesian are selected as benchmarks. these algorithms cover a general machine learning flow in object inference domain: feature extraction, feature selection and inference. the experimental results show that the proposed CGRA can gain 1443× average energy efficiency comparing to the Intel i7-3770 CPU and 7.82× energy efficiency comparing to a high performance FPGA solution [19].

关键词： Kernel Programming Reconfigurable architectures Energy efficiency Context Arrays

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