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检索条件"任意字段=Fourteenth Annual ACM Symposium on Parallel Algorithms and Architectures"

共 534 条记录，以下是61-70 订阅

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Brief announcement: Energy optimization of memory intensive parallel workloads 16

Brief announcement: Energy optimization of memory intensive ...

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28th acm symposium on parallelism in algorithms and architectures, SPAA 2016

作者： Trehan, Chhaya Vandierendonck, Hans Karakonstantis, Georgios Nikolopoulos, Dimitrios S. Queen's University Belfast United Kingdom

ISBN: (纸本)9781450342100

Energy consumption is an important concern in modern multicore processors. The energy consumed during the execution of an application can be minimized by tuning the hardware state utilizing knobs such as frequency, voltage etc. The existing theoretical work on energy minimization using Global DVFS (Dynamic Voltage and Frequency Scaling), despite being thorough, ignores the energy consumed by the CPU on memory accesses and the dynamic energy consumed by the idle cores. This article presents an analytical energy-performance model for parallel workloads that accounts for the energy consumed by the CPU chip on memory accesses in addition to the energy consumed on CPU instructions. In addition, the model we present also accounts for the dynamic energy consumed by the idle cores. We present an analytical framework around our energy-performance model to predict the operating frequencies for global DVFS that minimize the overall CPU energy consumption. We show how the optimal frequencies in our model differ from the optimal frequencies in a model that does not account for memory accesses. We further show how the memory intensity of an application affects the optimal frequencies.

关键词： Energy utilization

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Shuffles and Circuits (On Lower Bounds for Modern parallel Computation) 16

Shuffles and Circuits (On Lower Bounds for Modern Parallel C...

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28th acm symposium on parallelism in algorithms and architectures, SPAA 2016

作者： Roughgarden, Tim Vassilvitskii, Sergei Wang, Joshua R. Google Inc. United States

ISBN: (纸本)9781450342100

The goal of this paper is to identify fundamental limitations on how efficiently algorithms implemented on platforms such as MapReduce and Hadoop can compute the central problems in the motivating application domains, such as graph connectivity problems. We introduce an abstract model of massively parallel computation, where essentially the only restrictions are that the "fan-in" of each machine is limited to s bits, where s is smaller than the input size n, and that computation proceeds in synchronized rounds, with no communication between different machines within a round. Lower bounds on the round complexity of a problem in this model apply to every computing platform that shares the most basic design principles of MapReduce-type systems. We prove that computations in our model that use few rounds can be represented as low-degree polynomials over the reals. This connection allows us to translate a lower bound on the (approximate) polynomial degree of a Boolean function to a lower bound on the round complexity of every (randomized) massively parallel computation of that function. These lower bounds apply even in the "unbounded width" version of our model, where the number of machines can be arbitrarily large. As one example of our general results, computing any non-trivial monotone graph property - such as connectivity - requires a super-constant number of rounds when every machine can accept only a sub-polynomial (in n) number of input bits s. Finally, we prove that, in two senses, our lower bounds are the best one could hope for. For the unbounded-width model, we prove a matching upper bound. Restricting to a polynomial number of machines, we show that asymptotically better lower bounds require proving that P ≠ NC1.

关键词： MapReduce

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parallel shortest paths using radius stepping 16

Parallel shortest paths using radius stepping

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28th acm symposium on parallelism in algorithms and architectures, SPAA 2016

作者： Blelloch, Guy E. Gu, Yan Sun, Yihan Tangwongsan, Kanat Carnegie Mellon University United States Mahidol University International College Thailand

ISBN: (纸本)9781450342100

The single-source shortest path problem (SSSP) with nonnegative edge weights is notoriously difficult to solve efficiently in parallel-it is one of the graph problems said to suffer from the transitive-closure bottleneck. Yet, in practice, the Δ-stepping algorithm of Meyer and Sanders (J. algorithms, 2003) often works efficiently but has no known theoretical bounds on general graphs. The algorithm takes a sequence of steps, each increasing the radius by a user-specified value Δ. Each step settles the vertices in its annulus but can take θ(n) substeps, each requiring θ(m) work (n vertices and m edges). Building on the success of Δ-stepping, this paper describes Radius-Stepping, an algorithm with one of the best-known tradeoffs between work and depth bounds for SSSP with nearly-linear (Õ(m)) work. The algorithm is a Δ-stepping-like algorithm but uses a variable instead of a fixed-size increase in radii, allowing us to prove a bound on the number of steps. In particular, by using what we define as a vertex k-radius, each step takes at most k + 2 substeps. Furthermore, we define a pk, ρ)-graph property and show that if an undirected graph has this property, then the number of steps can be bounded by Opn/ρ · log ρL), for a total of Opkn/ρ · logρL) substeps, each parallel. We describe how to preprocess a graph to have this property. Altogether, for an arbitrary input graph with n vertices and m edges, Radius-Stepping, after preprocessing, takes Oppm+nρ) logn) work and On/ρ-logn log p ρL)) depth per source. The preprocessing step takes p mlogn + nρ2) work and O pρ log ρ) depth, adding no more than Opnρ) edges. © 2016 acm.

关键词： Undirected graphs

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Extending the nested parallel model to the nested dataflow model with provably efficient schedulers 16

Extending the nested parallel model to the nested dataflow m...

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28th acm symposium on parallelism in algorithms and architectures, SPAA 2016

作者： Dinh, David Simhadri, Harsha Vardhan Tang, Yuan Computer Science Division Univ. of California Berkeley BerkeleyCA94720 United States Computer Science Dept. Lawrence Berkeley National Lab. BerkeleyCA94720 United States School of Software Fudan Univ. Shanghai Key Lab. of Intelligent Information Processing Shanghai200433 China

ISBN: (纸本)9781450342100

The nested parallel (a.k.a. fork-join) model is widely used for writing parallel programs. However, the two composition constructs, i.e. "k" (parallel) and "k" (serial), that comprise the nested-parallel model are insufficient in expressing "partial dependencies" in a program. We propose a new dataflow composition construct "" to express partial dependencies in algorithms in a processorand cache-oblivious way, thus extending the Nested parallel (NP) model to the Nested Dataflow (ND) model. We redesign several divide-and-conquer algorithms ranging from dense linear algebra to dynamic-programming in the ND model and prove that they all have optimal span while retaining optimal cache complexity. We propose the design of runtime schedulers that map ND programs to multicore processors with multiple levels of possibly shared caches (i.e, parallel Memory Hierarchies) and prove guarantees on their ability to balance nodes across processors and preserve locality. For this, we adapt space-bounded (SB) schedulers for the ND model. We show that our algorithms have increased "parallelizability" in the ND model, and that SB schedulers can use the extra parallelizability to achieve asymptotically optimal bounds on cache misses and running time on a greater number of processors than in the NP model. The running time for the algorithms in this paper is(Equation presented on a p-processor machine, where Q∗ is the parallel cache complexity of task t, Ci is the cost of cache miss at level-i cache which is of size Mi, and σ ∈ (0,1) is a constant.

关键词： parallel processing systems

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KLAP: Kernel launch aggregation and promotion for optimizing dynamic parallelism 49

KLAP: Kernel launch aggregation and promotion for optimizing...

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IEEE/acm International symposium on Microarchitecture (MICRO)

作者： Izzat El Hajj Juan Gomez-Luna Cheng Li Li-Wen Chang Dejan Milojicic Wen-mei Hwu University of Illinois College of Law Champaign IL US Universidad de C??rdoba University of Illinois at Urbana-Champaign IL USA Hewlett-Packard Labs

ISBN: (纸本)9781509035090

Dynamic parallelism on GPUs simplifies the programming of many classes of applications that generate paral-lelizable work not known prior to execution. However, modern GPUs architectures do not support dynamic parallelism efficiently due to the high kernel launch overhead, limited number of simultaneous kernels, and limited depth of dynamic calls a device can support. In this paper, we propose Kernel Launch Aggregation and Promotion (KLAP), a set of compiler techniques that improve the performance of kernels which use dynamic parallelism. Kernel launch aggregation fuses kernels launched by threads in the same warp, block, or kernel into a single aggregated kernel, thereby reducing the total number of kernels spawned and increasing the amount of work per kernel to improve occupancy. Kernel launch promotion enables early launch of child kernels to extract more parallelism between parents and children, and to aggregate kernel launches across generations mitigating the problem of limited depth. We implement our techniques in a real compiler and show that kernel launch aggregation obtains a geometric mean speedup of 6.58x over regular dynamic parallelism. We also show that kernel launch promotion enables cases that were not originally possible, improving throughput by a geometric mean of 30.44 x.

关键词： Kernel parallel processing Graphics processing units Heuristic algorithms Synchronization Hardware Fuses

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annual acm symposium on parallelism in algorithms and architectures

Annual ACM Symposium on Parallelism in Algorithms and Archit...

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27th acm symposium on parallelism in algorithms and architectures, SPAA 2015

ISBN: (纸本)9781450335881

The proceedings contain 42 papers. The topics discussed include: sorting with asymmetric read and write costs;myths and misconceptions about threads;new streaming algorithms for parameterized maximal matching & beyond;efficient approximation algorithms for computing k disjoint restricted shortest paths;fast and better distributed MapReduce algorithms for k-center clustering;fair adaptive parallelism for concurrent transactional memory applications;towards a universal approach for the finite departure problem in overlay networks;a compiler-runtime application binary interface for pipe-while loops;the Cilkprof scalability profiler;efficiently detecting races in Cilk programs that use reducer hyperobjects;ThreadScan: automatic and scalable memory reclamation;temporal fairness of round robin: competitive analysis for Lk-norms of flow time;and space and time efficient parallel graph decomposition, clustering, and diameter approximation.

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Proceedings of the annual International symposium on Microarchitecture, MICRO

Proceedings of the Annual International Symposium on Microar...

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47th annual IEEE/acm International symposium on Microarchitecture, MICRO 2014

The proceedings contain 53 papers. The topics discussed include: transparent hardware management of stacked DRAM as part of memory;unison cache: a scalable and effective die-stacked DRAM cache;locality-aware mapping of nested parallel patterns on GPUs;accelerating irregular algorithms on GPGPUs using fine-grain hardware worklists;exploring the design space of SPMD divergence management on data-parallel architectures;managing GPU concurrency in heterogeneous architectures;FIRM: fair and high-performance memory control for persistent memory systems;efficient memory virtualization: reducing dimensionality of nested page walks;Iso-X: a flexible architecture for hardware-managed isolated execution;cc-hunter: uncovering covert timing channels on shared processor hardware;a practical methodology for measuring the side-channel signal available to the attacker for instruction-level events;and calculating architectural vulnerability factors for spatial multi-bit transient faults.

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Exploring the Design Space of SPMD Divergence Management on Data-parallel architectures 47

Exploring the Design Space of SPMD Divergence Management on ...

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47th annual IEEE/acm International symposium on Microarchitecture (MICRO)

作者： Lee, Yunsup Grover, Vinod Krashinsky, Ronny Stephenson, Mark Keckler, Stephen W. Asanovic, Krste Univ Calif Berkeley Berkeley CA 94720 USA NVIDIA Santa Clara CA USA Univ Texas Austin Austin TX 78712 USA

ISBN: (纸本)9781479969982

Data-parallel architectures must provide efficient support for complex control-flow constructs to support sophisticated applications coded in modern single-program multiple-data languages. As these architectures have wide datapaths that process a single instruction across parallel threads, a mechanism is needed to track and sequence threads as they traverse potentially divergent control paths through the program. The design space for divergence management ranges from software-only approaches where divergence is explicitly managed by the compiler, to hardware solutions where divergence is managed implicitly by the microarchitecture. In this paper, we explore this space and propose a new predication-based approach for handling control-flow structures in data-parallel architectures. Unlike prior predication algorithms, our new compiler analyses and hardware instructions consider the commonality of predication conditions across threads to improve efficiency. We prototype our algorithms in a production compiler and evaluate the tradeoffs between software and hardware divergence management on current GPU silicon. We show that our compiler algorithms make a predication-only architecture competitive in performance to one with hardware support for tracking divergence.

关键词： Vectors Hardware Computer architecture Registers Optimization Software Support vector machines

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SPAA 2014 - Proceedings of the 26th acm symposium on parallelism in algorithms and architectures

SPAA 2014 - Proceedings of the 26th ACM Symposium on Paralle...

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26th acm symposium on parallelism in algorithms and architectures, SPAA 2014

ISBN: (纸本)9781450328210

The proceedings contain 42 papers. The topics discussed include: on dynamic bin packing for resource allocation in the cloud;on the online fault-tolerant server consolidation problem;on computing maximal independent sets of hypergraphs in parallel;simple parallel and distributed algorithms for spectral graph sparsification;concurrent data structures for efficient streaming aggregation;provably good scheduling for parallel programs that use data structures through implicit batching;scheduling selfish jobs on multidimensional parallel machines;LP rounding and combinatorial algorithms for minimizing active and busy time;a note on multiprocessor speed scaling with precedence constraints;executing dynamic data-graph computations deterministically using chromatic scheduling;the PCL theorem. transactions cannot be parallel, consistent and live;adaptive integration of hardware and software lock elision techniques;and transaction-friendly condition variables.

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Efficient dynamic scheduling of heterogeneous applications in hybrid architectures 14

Efficient dynamic scheduling of heterogeneous applications i...

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29th annual acm symposium on Applied Computing, SAC 2014

作者： Andrade, Guilherme Ramos, Gabriel Madeira, Daniel Sachetto, Rafael Clua, Esteban Ferreira, Renato Rocha, Leonardo Universidade Federal de São João Del Rey Computer Science São João Del Rei Brazil Universidade Federal de Minas Gerais Computer Science Belo Horizonte Brazil Universidade Federal Fluminense Computer Science Niterói Brazil

ISBN: (纸本)9781450324694

The emergence of different applications that deal with growing amounts of data at reasonable times, has stimulated the development of new computing architectures consisting of different processing units (PU). Runtime environments have been proposed in order to exploit these resource as much as possible by offering a variety of methods for dynamically scheduling tasks on different PUs. These schedulers determine which PU is better suited for executing each task, based upon a set of task parameters such as the amount of data, computation requirements, etc. Although large number of applications are heterogeneous, composed of tasks with different characteristics, the current techniques focus on these characteristics as isolated features leading to inefficient executions in several situations. In this work we present two new scheduling strategies, combining different existing strategies, that leads to more efficient executions in different scenarios. Our results show that our approach can be up to 20% more efficient than current techniques. Copyright 2014 acm.

关键词： parallel algorithms

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