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distributed classification using class-association rules mining algorithm

Distributed classification using class-association rules min...

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international conference on Machine and Web Intelligence

作者： Mokeddem, Djamila Belbachir, Hafida Dept. of Computer Sciences LSSD Laboratory University of Sciences and Technologies Mohamed Boudiaf Oran Algeria

ISBN: (纸本)9781424486113

Associative classification algorithms have been successfully used to construct classification systems. The major strength of such techniques is that they are able to use the most accurate rules among an exhaustive list of class-association rules. This explains their good performance in general, but to the detriment of an expensive computing cost, inherited from association rules discovery algorithms. We address this issue by proposing a distributed methodology based on FP-growth algorithm. In a shared nothing architecture, subsets of classification rules are generated in parallel from several data partitions. An inter-processor communication is established in order to make global decisions. This exchange is made only in the first level of recursion, allowing each machine to subsequently process all its assigned tasks independently. The final classifier is built by a majority vote. This approach is illustrated by a detailed example, and an analysis of communication cost. © 2010 IEEE.

关键词： Association rules

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Achieving flow-level controllability in network intrusion detection system

Achieving flow-level controllability in network intrusion de...

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11th ACIS international conference on Software Engineering, Artificial Intelligence, Networking and parallel/distributed computing, SNPD2010

作者： Song, Bo Yang, Weibing Chen, Mingyu Zhao, Xiaofang Fan, Jianping Institute of Computing Technology Chinese Academy of Sciences China Graduate School of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769540887

Current network intrusion detection systems are lack of controllability, manifested as significant packet loss due to the long-term resources occupation by a single flow. The reasons can be classified into two kinds. The first kind is known as normal reasons, that is, the processing of mass arriving packets of a large flow can not be limited to a determinable period of time and thus makes other flows starved. The second kind, in which the CPU is trapped in a dead-loop like state due to processing some packets with particular content of a flow, is considered as abnormal reasons. In fact, it is a kind of software crashes. In this paper, we discuss the innate defects of traditional packet-driven NIDS, and implement a flow-driven framework which can achieve finegrained controllability. An Active Two-threshold scheme based on ideal Exit-Point (ATEP) is proposed in order to diminish data preserving overhead during flow switches and to detect crash in time. A quick crash recovery mechanism is also given which can recover the trapped thread from 90% crashes in 0.2ms. The experimental results show that our flow-driven framework with ATEP scheme can achieve higher throughput and less packet loss ratio than the uncontrollable packet-driven systems with less than 1% of extra CPU overhead. What's more, in the case of crash occurrence, the ATEP scheme is still able to maintain rather steady throughput without sudden decrease. © 2010 IEEE.

关键词： Controllability

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parallel simultaneous co-clustering and learning with map-reduce

Parallel simultaneous co-clustering and learning with map-re...

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IEEE international conference on Granular computing

作者： Deodhar, Meghana Jones, Clinton Ghosh, Joydeep Electrical and Computer Engineering University of Texas at Austin Austin TX 78712 United States

ISBN: (纸本)9780769541617

Many data mining applications involve predictive modeling of very large, complex datasets. Such applications present a need for innovative algorithms and associated implementations that are not only effective in terms of prediction accuracy, but can also be efficiently run on distributed computational systems to yield results in reasonable time. This paper focuses on predictive modeling of multirelational data such as dyadic data with associated covariates or "side-information". We first give illustrative examples of applications that involve such data and then describe a general framework based on Simultaneous CO-clustering And Learning (SCOAL), which applies a divide-and-conquer approach to data analysis. We show that the main elements of the SCOAL algorithm can be effectively parallelized using the Map-Reduce framework. Experiments on Amazon's EC2 demonstrate that the proposed parallelizations result in considerable improvements in run time when using a cluster of machines. © 2010 IEEE.

关键词： Computational efficiency

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Kernel fusion: An effective method for better power efficiency on multithreaded GPU

Kernel fusion: An effective method for better power efficien...

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2010 IEEE/ACM international conference on Green computing and Communications, GreenCom 2010, 2010 IEEE/ACM international conference on Cyber, Physical and Social computing, CPSCom 2010

作者： Wang, Guibin Lin, YiSong Yi, Wei National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9780769543314

As one of the most popular accelerators, Graphics Processing Unit (GPU) has demonstrated high computing power in several application fields. On the other hand, GPU also produces high power consumption and has been one of the most largest power consumers in desktop and supercomputer systems. However, software power optimization method targeted for GPU has not been well studied. In this work, we propose kernel fusion method to reduce energy consumption and improve power efficiency on GPU architecture. Through fusing two or more independent kernels, kernel fusion method achieves higher utilization and much more balanced demand for hardware resources, which provides much more potential for power optimization, such as dynamic voltage and frequency scaling (DVFS). Basing on the CUDA programming model, this paper also gives several different fusion methods targeted for different situations. In order to make judicious fusion strategy, we deduce the process of fusing multiple independent kernels as a dynamic programming problem, which could be well solved with many existing tools and be simply embedded into compiler or runtime system. To reduce the overhead introduced by kernel fusion, we also propose effective method to reduce the usage of shared memory and coordinate the thread space of the kernels to be fused. Detailed experimental evaluation validates that the proposed kernel fusion method could reduce energy consumption without performance loss for several typical kernels. © 2010 IEEE.

关键词： Graphics processing unit

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A dynamic URL assignment method for parallel web crawler

A dynamic URL assignment method for parallel web crawler

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international conference on Computational Intelligence for Measurement systems and Applications

作者： Guerriero, A. Ragni, F. Martines, C. DEE Politecnico of Bari Bari Italy Joinet S.r.l. Taranto Italy

ISBN: (纸本)9781424472291

A web crawler is a relatively simple automated program or script that methodically scans or "crawls" through Internet pages to retrieval information from data. Alternative names for a web crawler include web spider, web robot, bot, crawler, and automatic indexer. There are many different uses for a web crawler. Their primary purpose is to collect data so that when Internet surfers enter a search term on their site, they can quickly provide the surfer with relevant web sites. In this work we propose the model of a low cost web crawler for distributed environments based on an efficient URL assignment algorithm. The function of every module of the crawler is analyzed and main rules that crawlers must follow to maintain load balancing and robustness of system when they are searching on the web simultaneously, are discussed. The proposed adynamic URL assignment method, based on grid computing technology and dynamic clustering, results efficient increasing web crawler performance. © 2010 IEEE.

关键词： Cache memory

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parallel Variable-Length Encoding on GPGPUs

Parallel Variable-Length Encoding on GPGPUs

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15th international Euro-Par conference on parallel computing

作者： Balevic, Ana Univ Stuttgart D-7000 Stuttgart Germany

ISBN: (纸本)9783642141218

Variable-Length Encoding (VLE) is a process of reducing input data size by replacing fixed-length data words with codewords of shorter length. As VLE is one of the main building blocks in systems for multimedia compression, its efficient implementation is essential. The massively parallel architecture of modern general purpose graphics processing units (CPGPUs) has been successfully used for acceleration of inherently parallel compression blocks, such as image transforms and motion estimation. On the other hand, VLE is an inherently serial process due to the requirement of writing a variable number of bits for each codeword to the compressed data stream. The introduction of the atomic operations on the latest CPGPUs enables writing to the output memory locations by many threads in parallel. We present a novel data parallel algorithm for variable length encoding using atomic operations, which archives performance speedups of up to 35-50x using a CUDA-enabled GPGPU.

关键词： Program processors

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A Dynamic, distributed, Hierarchical Load Balancing for HLA-Based Simulations on Large-Scale Environments

A Dynamic, Distributed, Hierarchical Load Balancing for HLA-...

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16th international Euro-Par conference on parallel Processing

作者： De Grande, Robson Eduardo Boukerche, Azzedine Univ Ottawa Sch Informat Technol & Engn Ottawa ON K1N 6N5 Canada

ISBN: (纸本)9783642152764

The dynamic management of load in large-scale distributed systems is essential for the performance of simulations due to the influence that computing capacity and work load have on execution time. The High Level Architecture (HLA) was designed with the purpose of providing management services in order to organize distributed simulations, but the framework does not offer tools for controlling load imbalances of distributed simulations. In order to provide a generic solution for the simulation load imbalances, many approaches have been proposed. These schemes are limited to solve balancing issues regarding specific simulation or environment characteristics. With focus on balancing the computational load specially for HLA-based simulations, an approach have been previously proposed based on a centralized method, but this solution performs load re-distributions based on a central element, introducing global synchronization in the system. Therefore, avoiding the issues caused by centralization, a distributed, hierarchical balancing design is proposed to dynamically organize the load through three phases: monitoring, redistribution, and migration. The proposed scheme addresses improvement of fault tolerance, decrease of balancing overhead, and reduction of delays and bottlenecks, while exhibiting performance similar to the centralized approach in the experiments.

关键词： Fault tolerance

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Integrating Autonomic Grid Components and Process-Driven Business Applications

Integrating Autonomic Grid Components and Process-Driven Bus...

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3rd international ICST conference on Autonomic computing and Communication systems, Autonomics 2009

作者： Weigold, Thomas Aldinucci, Marco Danelutto, Marco Getov, Vladimir IBM Zurich Res Lab Zurich Switzerland Univ Turin Dept Comp Sci I-10124 Turin Italy Univ Pisa Dept Comp Sci I-56100 Pisa Italy Univ Westminster Sch Elect & Comp Sci London W1R 8AL England

ISBN: (纸本)9783642114816

Today's business applications are increasingly process driven, meaning that the main application logic is executed by a dedicate process engine. In addition, component-oriented software development has been attracting attention for building complex distributed applications. In this paper we present the experiences gained from building a process-driven biometric identification application which makes use of Grid infrastructures via the Grid Component Model (GCM). GCM, besides guaranteeing access to Grid resources, supports autonomic management of notable parallel composite components. This feature is exploited within our biometric identification application to ensure real time identification of fingerprints. Therefore, we briefly introduce the GCM framework and the process engine used, and we describe the implementation of the application using autonomic GCM components. Finally, we summarize the results, experiences, and lessons learned focusing on the integration of autonomic GCM components and the process-driven approach.

关键词： Autonomic computing components parallel applications distributed applications process-driven applications

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Power analysis and optimizations for GPU architecture using a power simulator

Power analysis and optimizations for GPU architecture using ...

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2010 3rd international conference on Advanced Computer Theory and Engineering, ICACTE 2010

作者： Wang, Guibin National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9781424465408

As one of the most popular many-core architecture, GPUs have illustrated power in many non-graphic applications. Traditional general purpose computing systems tend to integrate GPU as the co-processor to accelerate parallel computing tasks. Meanwhile, GPUs also result in high power consumption, which accounts for a large proportion of the total system power consumption. In this paper, we mainly focus on the power analysis and optimizations for GPU architecture. The main contributions of this paper are: firstly, we establish a GPU power reserach platform, which is extended from an existing GPU simulator with several power models;secondly, we validate that, as the gap between shader core and memory speed becomes larger and larger, integrating more shader cores or enhancing running frequencies may not bring better performance, but results in higher energy consumption;thirdly, we show that traditional power optimization methods for CPUs, such as dynamic frequency scaling and concurrencythrottling, could be effectively applied on GPU architectures for better power efficiency, especially for memory-intensive applications. © 2010 IEEE.

关键词： Simulators

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Evaluation of streaming aggregation on parallel hardware architectures 10

Evaluation of streaming aggregation on parallel hardware arc...

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4th ACM international conference on distributed Event-Based systems, DEBS 2010

作者： Schneidert, Scott Andrade, Henrique Gedik, Buǧra Wu, Kun-Lung Nikolopoulos, Dimitrios S. Virginia Tech. Department of Computer Science Blacksburg VA United States T.J. Watson Research Center IBM Research Hawthorne NY United States Institute for Computer Science Foundation for Research and Technology - Hellas Heraklion Greece

ISBN: (纸本)9781605589275

We present a case study parallelizing streaming aggregation on three different parallel hardware architectures. Aggregation is a performance-critical operation for data summarization in stream computing, and is commonly found in sense-and-respond applications. Currently available commodity parallel hardware provides promise as accelerators for streaming aggregation. However, how streaming aggregation can map to the different parallel architectures is still an open question. Streaming aggregation is obviously data parallel, but in practice its performance relies more on efficient data movement than computation, as we will demonstrate. Furthermore, we used workloads such as stock market data, which introduces unique data distribution problems. The three parallel architectures we use in our study are an Intel Core 2 Quad processor, an Nvidia GTX 285 GPU and the IBM PowerXCell 8i, an enhanced version of the Cell Broadband Engine architecture. Our implementations use OpenMP, CUDA and Cellgen (a compiler for OpenMP-like support on Cell) respectively. We find that the Cell's programmable local storage, and its low latency, high bandwidth access to main memory are best suited for parallelizing streaming aggregation. GPUs in the future can overcome the latency and bandwidth limitations by being fully integrated in the system's memory hierarchy. In order to attain good performance on existing parallel architectures, we find that developers must characterize their problem in terms of communication versus computation costs;memory access patterns, including assessing whether their algorithms reuse data;and the granularity of data access patterns. © 2010 ACM.

关键词： parallel architectures

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